ath/ath12k/hal_rx.c

220 int ath12k_hal_reo_cmd_send(struct ath12k_base *ab, struct hal_srng *srng,
229 	ath12k_hal_srng_access_begin(ab, srng);
230 	reo_desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
241 		ret = ath12k_hal_reo_cmd_flush_cache(&ab->hal, reo_desc, cmd);
249 		ath12k_warn(ab, "Unsupported reo command %d\n", type);
253 		ath12k_warn(ab, "Unknown reo command %d\n", type);
259 	ath12k_hal_srng_access_end(ab, srng);
317 int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab,
329 	ab->soc_stats.reo_error[err_code]++;
333 		ath12k_warn(ab, "expected error push reason code, received %d\n",
340 		ath12k_warn(ab, "expected buffer type link_desc");
344 	ath12k_hal_rx_reo_ent_paddr_get(ab, &desc->buf_addr_info, paddr, &cookie);
350 int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc,
384 			ab->soc_stats.invalid_rbm++;
396 			ab->soc_stats.invalid_rbm++;
438 void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab,
449 void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab,
462 void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv,
475 	ath12k_dbg(ab, ATH12K_DBG_HAL, "Queue stats status:\n");
476 	ath12k_dbg(ab, ATH12K_DBG_HAL, "header: cmd_num %d status %d\n",
479 	ath12k_dbg(ab, ATH12K_DBG_HAL, "ssn %u cur_idx %u\n",
484 	ath12k_dbg(ab, ATH12K_DBG_HAL, "pn = [%08x, %08x, %08x, %08x]\n",
486 	ath12k_dbg(ab, ATH12K_DBG_HAL, "last_rx: enqueue_tstamp %08x dequeue_tstamp %08x\n",
489 	ath12k_dbg(ab, ATH12K_DBG_HAL, "rx_bitmap [%08x %08x %08x %08x %08x %08x %08x %08x]\n",
493 	ath12k_dbg(ab, ATH12K_DBG_HAL, "count: cur_mpdu %u cur_msdu %u\n",
498 	ath12k_dbg(ab, ATH12K_DBG_HAL, "fwd_timeout %u fwd_bar %u dup_count %u\n",
505 	ath12k_dbg(ab, ATH12K_DBG_HAL, "frames_in_order %u bar_rcvd %u\n",
510 	ath12k_dbg(ab, ATH12K_DBG_HAL, "num_mpdus %d num_msdus %d total_bytes %d\n",
513 	ath12k_dbg(ab, ATH12K_DBG_HAL, "late_rcvd %u win_jump_2k %u hole_cnt %u\n",
520 	ath12k_dbg(ab, ATH12K_DBG_HAL, "looping count %u\n",
525 void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv,
542 void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv,
545 	struct ath12k_hal *hal = &ab->hal;
583 void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv,
586 	struct ath12k_hal *hal = &ab->hal;
610 void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab,
639 void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab,
674 void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab,
794 void ath12k_hal_reo_init_cmd_ring(struct ath12k_base *ab,
806 	entry_size = ath12k_hal_srng_get_entrysize(ab, HAL_REO_CMD);
807 	ath12k_hal_srng_get_params(ab, srng, &params);
819 void ath12k_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map)
824 	val = ath12k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
828 	ath12k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
830 	val = ath12k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(ab));
838 	ath12k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(ab), val);
840 	ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
842 	ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
844 	ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
846 	ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
849 	ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
851 	ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,