Lines Matching refs:ab
17 static void ath12k_dp_htt_htc_tx_complete(struct ath12k_base *ab,
25 struct ath12k_base *ab = ar->ab;
30 spin_lock_bh(&ab->base_lock);
31 peer = ath12k_peer_find(ab, vdev_id, addr);
33 ath12k_warn(ab, "failed to lookup peer %pM on vdev %d\n",
35 spin_unlock_bh(&ab->base_lock);
42 spin_unlock_bh(&ab->base_lock);
47 struct ath12k_base *ab = ar->ab;
59 ath12k_warn(ab, "failed to set default routing %d peer :%pM vdev_id :%d\n",
68 ath12k_warn(ab, "failed to setup rxd tid queue for tid %d: %d\n",
76 ath12k_warn(ab, "failed to setup rx defrag context\n");
85 spin_lock_bh(&ab->base_lock);
87 peer = ath12k_peer_find(ab, vdev_id, addr);
89 ath12k_warn(ab, "failed to find the peer to del rx tid\n");
90 spin_unlock_bh(&ab->base_lock);
97 spin_unlock_bh(&ab->base_lock);
102 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring)
107 dma_free_coherent(ab->dev, ring->size, ring->vaddr_unaligned,
127 static int ath12k_dp_srng_calculate_msi_group(struct ath12k_base *ab,
135 grp_mask = &ab->hw_params->ring_mask->rx_wbm_rel[0];
138 grp_mask = &ab->hw_params->ring_mask->tx[0];
142 grp_mask = &ab->hw_params->ring_mask->rx_err[0];
145 grp_mask = &ab->hw_params->ring_mask->rx[0];
148 grp_mask = &ab->hw_params->ring_mask->reo_status[0];
152 grp_mask = &ab->hw_params->ring_mask->rx_mon_dest[0];
155 grp_mask = &ab->hw_params->ring_mask->tx_mon_dest[0];
158 grp_mask = &ab->hw_params->ring_mask->host2rxdma[0];
178 static void ath12k_dp_srng_msi_setup(struct ath12k_base *ab,
186 ret = ath12k_hif_get_user_msi_vector(ab, "DP",
192 msi_group_number = ath12k_dp_srng_calculate_msi_group(ab, type,
195 ath12k_dbg(ab, ATH12K_DBG_PCI,
204 ath12k_dbg(ab, ATH12K_DBG_PCI,
209 ath12k_hif_get_msi_address(ab, &addr_lo, &addr_hi);
218 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring,
223 int entry_sz = ath12k_hal_srng_get_entrysize(ab, type);
224 int max_entries = ath12k_hal_srng_get_max_entries(ab, type);
234 ring->vaddr_unaligned = dma_alloc_coherent(ab->dev, ring->size,
247 ath12k_dp_srng_msi_setup(ab, ¶ms, type, ring_num + mac_id);
270 if (ab->hw_params->hw_ops->dp_srng_is_tx_comp_ring(ring_num)) {
298 ath12k_warn(ab, "Not a valid ring type in dp :%d\n", type);
302 ret = ath12k_hal_srng_setup(ab, type, ring_num, mac_id, ¶ms);
304 ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n",
315 u32 ath12k_dp_tx_get_vdev_bank_config(struct ath12k_base *ab, struct ath12k_vif *arvif)
323 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags))
353 static int ath12k_dp_tx_get_bank_profile(struct ath12k_base *ab, struct ath12k_vif *arvif,
362 bank_config = ath12k_dp_tx_get_vdev_bank_config(ab, arvif);
381 ath12k_err(ab, "unable to find TX bank!");
394 ath12k_hal_tx_configure_bank_register(ab, bank_config, bank_id);
396 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt tcl bank_id %d input 0x%x match 0x%x num_users %u",
410 static void ath12k_dp_deinit_bank_profiles(struct ath12k_base *ab)
412 struct ath12k_dp *dp = &ab->dp;
418 static int ath12k_dp_init_bank_profiles(struct ath12k_base *ab)
420 struct ath12k_dp *dp = &ab->dp;
421 u32 num_tcl_banks = ab->hw_params->num_tcl_banks;
441 static void ath12k_dp_srng_common_cleanup(struct ath12k_base *ab)
443 struct ath12k_dp *dp = &ab->dp;
446 ath12k_dp_srng_cleanup(ab, &dp->reo_status_ring);
447 ath12k_dp_srng_cleanup(ab, &dp->reo_cmd_ring);
448 ath12k_dp_srng_cleanup(ab, &dp->reo_except_ring);
449 ath12k_dp_srng_cleanup(ab, &dp->rx_rel_ring);
450 ath12k_dp_srng_cleanup(ab, &dp->reo_reinject_ring);
451 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
452 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_comp_ring);
453 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_data_ring);
455 ath12k_dp_srng_cleanup(ab, &dp->tcl_status_ring);
456 ath12k_dp_srng_cleanup(ab, &dp->tcl_cmd_ring);
457 ath12k_dp_srng_cleanup(ab, &dp->wbm_desc_rel_ring);
460 static int ath12k_dp_srng_common_setup(struct ath12k_base *ab)
462 struct ath12k_dp *dp = &ab->dp;
468 ret = ath12k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring,
472 ath12k_warn(ab, "failed to set up wbm2sw_release ring :%d\n",
477 ret = ath12k_dp_srng_setup(ab, &dp->tcl_cmd_ring, HAL_TCL_CMD, 0, 0,
480 ath12k_warn(ab, "failed to set up tcl_cmd ring :%d\n", ret);
484 ret = ath12k_dp_srng_setup(ab, &dp->tcl_status_ring, HAL_TCL_STATUS,
487 ath12k_warn(ab, "failed to set up tcl_status ring :%d\n", ret);
491 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
492 map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map;
495 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_data_ring,
499 ath12k_warn(ab, "failed to set up tcl_data ring (%d) :%d\n",
504 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_comp_ring,
508 ath12k_warn(ab, "failed to set up tcl_comp ring (%d) :%d\n",
514 ret = ath12k_dp_srng_setup(ab, &dp->reo_reinject_ring, HAL_REO_REINJECT,
517 ath12k_warn(ab, "failed to set up reo_reinject ring :%d\n",
522 ret = ath12k_dp_srng_setup(ab, &dp->rx_rel_ring, HAL_WBM2SW_RELEASE,
526 ath12k_warn(ab, "failed to set up rx_rel ring :%d\n", ret);
530 ret = ath12k_dp_srng_setup(ab, &dp->reo_except_ring, HAL_REO_EXCEPTION,
533 ath12k_warn(ab, "failed to set up reo_exception ring :%d\n",
538 ret = ath12k_dp_srng_setup(ab, &dp->reo_cmd_ring, HAL_REO_CMD,
541 ath12k_warn(ab, "failed to set up reo_cmd ring :%d\n", ret);
545 srng = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
546 ath12k_hal_reo_init_cmd_ring(ab, srng);
548 ret = ath12k_dp_srng_setup(ab, &dp->reo_status_ring, HAL_REO_STATUS,
551 ath12k_warn(ab, "failed to set up reo_status ring :%d\n", ret);
570 ath12k_hal_reo_hw_setup(ab, ring_hash_map);
575 ath12k_dp_srng_common_cleanup(ab);
580 static void ath12k_dp_scatter_idle_link_desc_cleanup(struct ath12k_base *ab)
582 struct ath12k_dp *dp = &ab->dp;
590 dma_free_coherent(ab->dev, HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX,
596 static int ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base *ab,
602 struct ath12k_dp *dp = &ab->dp;
616 ath12k_hal_srng_get_entrysize(ab, HAL_WBM_IDLE_LINK);
623 slist[i].vaddr = dma_alloc_coherent(ab->dev,
661 ath12k_hal_setup_link_idle_list(ab, slist, num_scatter_buf,
667 ath12k_dp_scatter_idle_link_desc_cleanup(ab);
673 ath12k_dp_link_desc_bank_free(struct ath12k_base *ab,
680 dma_free_coherent(ab->dev,
689 static int ath12k_dp_link_desc_bank_alloc(struct ath12k_base *ab,
694 struct ath12k_dp *dp = &ab->dp;
704 dma_alloc_coherent(ab->dev, desc_sz,
723 ath12k_dp_link_desc_bank_free(ab, dp->link_desc_banks);
728 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab,
732 ath12k_dp_link_desc_bank_free(ab, desc_bank);
735 ath12k_dp_srng_cleanup(ab, ring);
736 ath12k_dp_scatter_idle_link_desc_cleanup(ab);
740 static int ath12k_wbm_idle_ring_setup(struct ath12k_base *ab, u32 *n_link_desc)
742 struct ath12k_dp *dp = &ab->dp;
767 ret = ath12k_dp_srng_setup(ab, &dp->wbm_idle_ring,
770 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret);
776 int ath12k_dp_link_desc_setup(struct ath12k_base *ab,
810 ret = ath12k_dp_link_desc_bank_alloc(ab, link_desc_banks,
816 entry_sz = ath12k_hal_srng_get_entrysize(ab, ring_type);
822 ret = ath12k_dp_scatter_idle_link_desc_setup(ab, tot_mem_sz,
827 ath12k_warn(ab, "failed to setup scatting idle list descriptor :%d\n",
837 ath12k_hal_srng_access_begin(ab, srng);
846 (desc = ath12k_hal_srng_src_get_next_entry(ab, srng))) {
855 ath12k_hal_srng_access_end(ab, srng);
862 ath12k_dp_link_desc_bank_free(ab, link_desc_banks);
867 int ath12k_dp_service_srng(struct ath12k_base *ab,
879 while (i < ab->hw_params->max_tx_ring) {
880 if (ab->hw_params->ring_mask->tx[grp_id] &
881 BIT(ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[i].wbm_ring_num))
882 ath12k_dp_tx_completion_handler(ab, i);
886 if (ab->hw_params->ring_mask->rx_err[grp_id]) {
887 work_done = ath12k_dp_rx_process_err(ab, napi, budget);
894 if (ab->hw_params->ring_mask->rx_wbm_rel[grp_id]) {
895 work_done = ath12k_dp_rx_process_wbm_err(ab,
905 if (ab->hw_params->ring_mask->rx[grp_id]) {
906 i = fls(ab->hw_params->ring_mask->rx[grp_id]) - 1;
907 work_done = ath12k_dp_rx_process(ab, i, napi,
915 if (ab->hw_params->ring_mask->rx_mon_dest[grp_id]) {
917 ring_mask = ab->hw_params->ring_mask->rx_mon_dest[grp_id];
918 for (i = 0; i < ab->num_radios; i++) {
919 for (j = 0; j < ab->hw_params->num_rxmda_per_pdev; j++) {
920 int id = i * ab->hw_params->num_rxmda_per_pdev + j;
924 ath12k_dp_mon_process_ring(ab, id, napi, budget,
936 if (ab->hw_params->ring_mask->tx_mon_dest[grp_id]) {
938 ring_mask = ab->hw_params->ring_mask->tx_mon_dest[grp_id];
939 for (i = 0; i < ab->num_radios; i++) {
940 for (j = 0; j < ab->hw_params->num_rxmda_per_pdev; j++) {
941 int id = i * ab->hw_params->num_rxmda_per_pdev + j;
945 ath12k_dp_mon_process_ring(ab, id, napi, budget,
957 if (ab->hw_params->ring_mask->reo_status[grp_id])
958 ath12k_dp_rx_process_reo_status(ab);
960 if (ab->hw_params->ring_mask->host2rxdma[grp_id]) {
961 struct ath12k_dp *dp = &ab->dp;
964 ath12k_dp_rx_bufs_replenish(ab, rx_ring, 0);
973 void ath12k_dp_pdev_free(struct ath12k_base *ab)
977 del_timer_sync(&ab->mon_reap_timer);
979 for (i = 0; i < ab->num_radios; i++)
980 ath12k_dp_rx_pdev_free(ab, i);
983 void ath12k_dp_pdev_pre_alloc(struct ath12k_base *ab)
989 for (i = 0; i < ab->num_radios; i++) {
990 ar = ab->pdevs[i].ar;
1000 bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab)
1002 if (test_bit(WMI_TLV_SERVICE_WMSK_COMPACTION_RX_TLVS, ab->wmi_ab.svc_map) &&
1003 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start &&
1004 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end &&
1005 ab->hw_params->hal_ops->get_hal_rx_compact_ops) {
1011 void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab)
1013 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) {
1017 ab->hal_rx_ops = ab->hw_params->hal_ops->get_hal_rx_compact_ops();
1019 ab->hal.hal_desc_sz =
1020 ab->hal_rx_ops->rx_desc_get_desc_size();
1025 struct ath12k_base *ab = from_timer(ab, t, mon_reap_timer);
1028 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++)
1029 ath12k_dp_mon_process_ring(ab, i, NULL, DP_MON_SERVICE_BUDGET,
1032 mod_timer(&ab->mon_reap_timer, jiffies +
1036 static void ath12k_dp_mon_reap_timer_init(struct ath12k_base *ab)
1038 if (ab->hw_params->rxdma1_enable)
1041 timer_setup(&ab->mon_reap_timer, ath12k_dp_service_mon_ring, 0);
1044 int ath12k_dp_pdev_alloc(struct ath12k_base *ab)
1050 ret = ath12k_dp_rx_htt_setup(ab);
1054 ath12k_dp_mon_reap_timer_init(ab);
1057 for (i = 0; i < ab->num_radios; i++) {
1058 ar = ab->pdevs[i].ar;
1059 ret = ath12k_dp_rx_pdev_alloc(ab, i);
1061 ath12k_warn(ab, "failed to allocate pdev rx for pdev_id :%d\n",
1067 ath12k_warn(ab, "failed to initialize mon pdev %d\n", i);
1074 ath12k_dp_pdev_free(ab);
1091 status = ath12k_htc_connect_service(&dp->ab->htc, &conn_req,
1125 struct ath12k_base *ab = ar->ab;
1138 arvif->bank_id = ath12k_dp_tx_get_bank_profile(ab, arvif, &ab->dp);
1142 ath12k_err(ar->ab, "Failed to initialize DP TX Banks");
1147 static void ath12k_dp_cc_cleanup(struct ath12k_base *ab)
1151 struct ath12k_dp *dp = &ab->dp;
1169 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
1196 dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr,
1224 dma_free_coherent(ab->dev, ATH12K_PAGE_SIZE,
1232 static void ath12k_dp_reoq_lut_cleanup(struct ath12k_base *ab)
1234 struct ath12k_dp *dp = &ab->dp;
1236 if (!ab->hw_params->reoq_lut_support)
1242 dma_free_coherent(ab->dev, DP_REOQ_LUT_SIZE,
1246 ath12k_hif_write32(ab,
1247 HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab), 0);
1250 void ath12k_dp_free(struct ath12k_base *ab)
1252 struct ath12k_dp *dp = &ab->dp;
1255 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks,
1258 ath12k_dp_cc_cleanup(ab);
1259 ath12k_dp_reoq_lut_cleanup(ab);
1260 ath12k_dp_deinit_bank_profiles(ab);
1261 ath12k_dp_srng_common_cleanup(ab);
1263 ath12k_dp_rx_reo_cmd_list_cleanup(ab);
1265 for (i = 0; i < ab->hw_params->max_tx_ring; i++)
1268 ath12k_dp_rx_free(ab);
1272 void ath12k_dp_cc_config(struct ath12k_base *ab)
1274 u32 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
1279 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(ab), cmem_base);
1291 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG1(ab), val);
1294 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG0, cmem_base);
1304 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG1, val);
1307 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2);
1312 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2, val);
1315 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG);
1317 ab->hw_params->hal_params->wbm2sw_cc_enable;
1319 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG, val);
1327 static inline void *ath12k_dp_cc_get_desc_addr_ptr(struct ath12k_base *ab,
1330 struct ath12k_dp *dp = &ab->dp;
1335 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab,
1348 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx);
1353 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab,
1363 ppt_idx > ab->dp.num_spt_pages ||
1367 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx);
1372 static int ath12k_dp_cc_desc_init(struct ath12k_base *ab)
1374 struct ath12k_dp *dp = &ab->dp;
1400 rx_desc_addr = ath12k_dp_cc_get_desc_addr_ptr(ab, i, j);
1431 ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, j);
1440 static int ath12k_dp_cc_init(struct ath12k_base *ab)
1442 struct ath12k_dp *dp = &ab->dp;
1464 ath12k_warn(ab, "SPT page allocation failure");
1468 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
1471 dp->spt_info[i].vaddr = dma_alloc_coherent(ab->dev,
1482 ath12k_warn(ab, "SPT allocated memory is not 4K aligned");
1488 ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i),
1492 ret = ath12k_dp_cc_desc_init(ab);
1494 ath12k_warn(ab, "HW CC desc init failed %d", ret);
1500 ath12k_dp_cc_cleanup(ab);
1504 static int ath12k_dp_reoq_lut_setup(struct ath12k_base *ab)
1506 struct ath12k_dp *dp = &ab->dp;
1508 if (!ab->hw_params->reoq_lut_support)
1511 dp->reoq_lut.vaddr = dma_alloc_coherent(ab->dev,
1516 ath12k_warn(ab, "failed to allocate memory for reoq table");
1520 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab),
1525 int ath12k_dp_alloc(struct ath12k_base *ab)
1527 struct ath12k_dp *dp = &ab->dp;
1534 dp->ab = ab;
1542 ret = ath12k_wbm_idle_ring_setup(ab, &n_link_desc);
1544 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret);
1548 srng = &ab->hal.srng_list[dp->wbm_idle_ring.ring_id];
1550 ret = ath12k_dp_link_desc_setup(ab, dp->link_desc_banks,
1553 ath12k_warn(ab, "failed to setup link desc: %d\n", ret);
1557 ret = ath12k_dp_cc_init(ab);
1560 ath12k_warn(ab, "failed to setup cookie converter %d\n", ret);
1563 ret = ath12k_dp_init_bank_profiles(ab);
1565 ath12k_warn(ab, "failed to setup bank profiles %d\n", ret);
1569 ret = ath12k_dp_srng_common_setup(ab);
1575 ret = ath12k_dp_reoq_lut_setup(ab);
1577 ath12k_warn(ab, "failed to setup reoq table %d\n", ret);
1581 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
1597 ath12k_hal_tx_set_dscp_tid_map(ab, i);
1599 ret = ath12k_dp_rx_alloc(ab);
1608 ath12k_dp_rx_free(ab);
1611 ath12k_dp_reoq_lut_cleanup(ab);
1614 ath12k_dp_srng_common_cleanup(ab);
1617 ath12k_dp_deinit_bank_profiles(ab);
1620 ath12k_dp_cc_cleanup(ab);
1623 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks,