ath/ath11k/pcic.c

131 int ath11k_pcic_init_msi_config(struct ath11k_base *ab)
139 		if (msi_config->hw_rev == ab->hw_rev)
144 		ath11k_err(ab, "failed to fetch msi config, unsupported hw version: 0x%x\n",
145 			   ab->hw_rev);
149 	ab->pci.msi.config = msi_config;
154 static void __ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value)
157 		iowrite32(value, ab->mem  + offset);
159 		ab->pci.ops->window_write32(ab, offset, value);
162 void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value)
170 	wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
172 	if (wakeup_required && ab->pci.ops->wakeup)
173 		ret = ab->pci.ops->wakeup(ab);
175 	__ath11k_pcic_write32(ab, offset, value);
177 	if (wakeup_required && !ret && ab->pci.ops->release)
178 		ab->pci.ops->release(ab);
182 static u32 __ath11k_pcic_read32(struct ath11k_base *ab, u32 offset)
187 		val = ioread32(ab->mem + offset);
189 		val = ab->pci.ops->window_read32(ab, offset);
194 u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset)
203 	wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
205 	if (wakeup_required && ab->pci.ops->wakeup)
206 		ret = ab->pci.ops->wakeup(ab);
208 	val = __ath11k_pcic_read32(ab, offset);
210 	if (wakeup_required && !ret && ab->pci.ops->release)
211 		ab->pci.ops->release(ab);
217 int ath11k_pcic_read(struct ath11k_base *ab, void *buf, u32 start, u32 end)
227 	wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
229 	if (wakeup_required && ab->pci.ops->wakeup) {
230 		ret = ab->pci.ops->wakeup(ab);
232 			ath11k_warn(ab,
246 		*data++ = __ath11k_pcic_read32(ab, i);
248 	if (wakeup_required && ab->pci.ops->release)
249 		ab->pci.ops->release(ab);
255 void ath11k_pcic_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
258 	*msi_addr_lo = ab->pci.msi.addr_lo;
259 	*msi_addr_hi = ab->pci.msi.addr_hi;
263 int ath11k_pcic_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
267 	const struct ath11k_msi_config *msi_config = ab->pci.msi.config;
274 			*user_base_data = *base_vector + ab->pci.msi.ep_base_data;
276 			ath11k_dbg(ab, ATH11K_DBG_PCI,
285 	ath11k_err(ab, "Failed to find MSI assignment for %s!\n", user_name);
291 void ath11k_pcic_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx)
295 	for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
296 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
308 static void ath11k_pcic_free_ext_irq(struct ath11k_base *ab)
313 		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
316 			free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
322 void ath11k_pcic_free_irq(struct ath11k_base *ab)
326 	for (i = 0; i < ab->hw_params.ce_count; i++) {
327 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
330 		free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
333 	ath11k_pcic_free_ext_irq(ab);
337 static void ath11k_pcic_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
344 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
348 	enable_irq(ab->irq_num[irq_idx]);
351 static void ath11k_pcic_ce_irq_disable(struct ath11k_base *ab, u16 ce_id)
358 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
362 	disable_irq_nosync(ab->irq_num[irq_idx]);
365 static void ath11k_pcic_ce_irqs_disable(struct ath11k_base *ab)
369 	clear_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
371 	for (i = 0; i < ab->hw_params.ce_count; i++) {
372 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
374 		ath11k_pcic_ce_irq_disable(ab, i);
378 static void ath11k_pcic_sync_ce_irqs(struct ath11k_base *ab)
383 	for (i = 0; i < ab->hw_params.ce_count; i++) {
384 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
388 		synchronize_irq(ab->irq_num[irq_idx]);
397 	ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
399 	enable_irq(ce_pipe->ab->irq_num[irq_idx]);
405 	struct ath11k_base *ab = ce_pipe->ab;
408 	if (!test_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags))
414 	disable_irq_nosync(ab->irq_num[irq_idx]);
423 	struct ath11k_base *ab = irq_grp->ab;
429 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
433 		disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
436 static void __ath11k_pcic_ext_irq_disable(struct ath11k_base *ab)
440 	clear_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags);
443 		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
457 	struct ath11k_base *ab = irq_grp->ab;
463 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
467 		enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
470 void ath11k_pcic_ext_irq_enable(struct ath11k_base *ab)
475 		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
484 	set_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags);
488 static void ath11k_pcic_sync_ext_irqs(struct ath11k_base *ab)
493 		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
497 			synchronize_irq(ab->irq_num[irq_idx]);
502 void ath11k_pcic_ext_irq_disable(struct ath11k_base *ab)
504 	__ath11k_pcic_ext_irq_disable(ab);
505 	ath11k_pcic_sync_ext_irqs(ab);
514 	struct ath11k_base *ab = irq_grp->ab;
518 	work_done = ath11k_dp_service_srng(ab, irq_grp, budget);
522 			enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
534 	struct ath11k_base *ab = irq_grp->ab;
537 	if (!test_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))
540 	ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq %d\n", irq);
546 		disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
554 ath11k_pcic_get_msi_irq(struct ath11k_base *ab, unsigned int vector)
556 	return ab->pci.ops->get_msi_irq(ab, vector);
559 static int ath11k_pcic_ext_irq_config(struct ath11k_base *ab)
565 	ret = ath11k_pcic_get_user_msi_assignment(ab, "DP", &num_vectors,
572 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
576 		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
579 		irq_grp->ab = ab;
585 		if (ab->hw_params.ring_mask->tx[i] ||
586 		    ab->hw_params.ring_mask->rx[i] ||
587 		    ab->hw_params.ring_mask->rx_err[i] ||
588 		    ab->hw_params.ring_mask->rx_wbm_rel[i] ||
589 		    ab->hw_params.ring_mask->reo_status[i] ||
590 		    ab->hw_params.ring_mask->rxdma2host[i] ||
591 		    ab->hw_params.ring_mask->host2rxdma[i] ||
592 		    ab->hw_params.ring_mask->rx_mon_status[i]) {
602 			int irq = ath11k_pcic_get_msi_irq(ab, vector);
607 			ab->irq_num[irq_idx] = irq;
609 			ath11k_dbg(ab, ATH11K_DBG_PCI,
616 				ath11k_err(ab, "failed request irq %d: %d\n",
627 int ath11k_pcic_config_irq(struct ath11k_base *ab)
637 	ret = ath11k_pcic_get_user_msi_assignment(ab, "CE", &msi_data_count,
643 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
647 	for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
648 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
652 		irq = ath11k_pcic_get_msi_irq(ab, msi_data);
656 		ce_pipe = &ab->ce.ce_pipe[i];
665 			ath11k_err(ab, "failed to request irq %d: %d\n",
670 		ab->irq_num[irq_idx] = irq;
673 		ath11k_pcic_ce_irq_disable(ab, i);
676 	ret = ath11k_pcic_ext_irq_config(ab);
684 void ath11k_pcic_ce_irqs_enable(struct ath11k_base *ab)
688 	set_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
690 	for (i = 0; i < ab->hw_params.ce_count; i++) {
691 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
693 		ath11k_pcic_ce_irq_enable(ab, i);
698 static void ath11k_pcic_kill_tasklets(struct ath11k_base *ab)
702 	for (i = 0; i < ab->hw_params.ce_count; i++) {
703 		struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
705 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
712 void ath11k_pcic_ce_irq_disable_sync(struct ath11k_base *ab)
714 	ath11k_pcic_ce_irqs_disable(ab);
715 	ath11k_pcic_sync_ce_irqs(ab);
716 	ath11k_pcic_kill_tasklets(ab);
720 void ath11k_pcic_stop(struct ath11k_base *ab)
722 	ath11k_pcic_ce_irq_disable_sync(ab);
723 	ath11k_ce_cleanup_pipes(ab);
727 int ath11k_pcic_start(struct ath11k_base *ab)
729 	set_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
731 	ath11k_pcic_ce_irqs_enable(ab);
732 	ath11k_ce_rx_post_buf(ab);
738 int ath11k_pcic_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
745 	for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) {
746 		entry = &ab->hw_params.svc_to_ce_map[i];
782 int ath11k_pcic_register_pci_ops(struct ath11k_base *ab,
793 	ab->pci.ops = pci_ops;
798 void ath11k_pci_enable_ce_irqs_except_wake_irq(struct ath11k_base *ab)
802 	for (i = 0; i < ab->hw_params.ce_count; i++) {
803 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR ||
806 		ath11k_pcic_ce_irq_enable(ab, i);
811 void ath11k_pci_disable_ce_irqs_except_wake_irq(struct ath11k_base *ab)
817 	for (i = 0; i < ab->hw_params.ce_count; i++) {
818 		ce_pipe = &ab->ce.ce_pipe[i];
821 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR ||
825 		disable_irq_nosync(ab->irq_num[irq_idx]);
826 		synchronize_irq(ab->irq_num[irq_idx]);