ath/ath11k/pcic.c

131 int ath11k_pcic_init_msi_config(struct ath11k_base *ab)
139 		if (msi_config->hw_rev == ab->hw_rev)
144 		ath11k_err(ab, "failed to fetch msi config, unsupported hw version: 0x%x\n",
145 			   ab->hw_rev);
149 	ab->pci.msi.config = msi_config;
154 static void __ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value)
157 		iowrite32(value, ab->mem  + offset);
159 		ab->pci.ops->window_write32(ab, offset, value);
162 void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value)
170 	wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
172 	if (wakeup_required && ab->pci.ops->wakeup)
173 		ret = ab->pci.ops->wakeup(ab);
175 	__ath11k_pcic_write32(ab, offset, value);
177 	if (wakeup_required && !ret && ab->pci.ops->release)
178 		ab->pci.ops->release(ab);
182 static u32 __ath11k_pcic_read32(struct ath11k_base *ab, u32 offset)
187 		val = ioread32(ab->mem + offset);
189 		val = ab->pci.ops->window_read32(ab, offset);
194 u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset)
203 	wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
205 	if (wakeup_required && ab->pci.ops->wakeup)
206 		ret = ab->pci.ops->wakeup(ab);
208 	val = __ath11k_pcic_read32(ab, offset);
210 	if (wakeup_required && !ret && ab->pci.ops->release)
211 		ab->pci.ops->release(ab);
217 int ath11k_pcic_read(struct ath11k_base *ab, void *buf, u32 start, u32 end)
227 	wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
229 	if (wakeup_required && ab->pci.ops->wakeup) {
230 		ret = ab->pci.ops->wakeup(ab);
232 			ath11k_warn(ab,
246 		*data++ = __ath11k_pcic_read32(ab, i);
248 	if (wakeup_required && ab->pci.ops->release)
249 		ab->pci.ops->release(ab);
255 void ath11k_pcic_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
258 	*msi_addr_lo = ab->pci.msi.addr_lo;
259 	*msi_addr_hi = ab->pci.msi.addr_hi;
263 int ath11k_pcic_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
267 	const struct ath11k_msi_config *msi_config = ab->pci.msi.config;
274 			*user_base_data = *base_vector + ab->pci.msi.ep_base_data;
276 			ath11k_dbg(ab, ATH11K_DBG_PCI,
285 	ath11k_err(ab, "Failed to find MSI assignment for %s!\n", user_name);
291 void ath11k_pcic_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx)
295 	for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
296 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
308 static void ath11k_pcic_free_ext_irq(struct ath11k_base *ab)
313 		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
316 			free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
323 void ath11k_pcic_free_irq(struct ath11k_base *ab)
327 	for (i = 0; i < ab->hw_params.ce_count; i++) {
328 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
331 		free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
334 	ath11k_pcic_free_ext_irq(ab);
338 static void ath11k_pcic_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
345 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
349 	enable_irq(ab->irq_num[irq_idx]);
352 static void ath11k_pcic_ce_irq_disable(struct ath11k_base *ab, u16 ce_id)
359 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
363 	disable_irq_nosync(ab->irq_num[irq_idx]);
366 static void ath11k_pcic_ce_irqs_disable(struct ath11k_base *ab)
370 	clear_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
372 	for (i = 0; i < ab->hw_params.ce_count; i++) {
373 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
375 		ath11k_pcic_ce_irq_disable(ab, i);
379 static void ath11k_pcic_sync_ce_irqs(struct ath11k_base *ab)
384 	for (i = 0; i < ab->hw_params.ce_count; i++) {
385 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
389 		synchronize_irq(ab->irq_num[irq_idx]);
398 	ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
400 	enable_irq(ce_pipe->ab->irq_num[irq_idx]);
406 	struct ath11k_base *ab = ce_pipe->ab;
409 	if (!test_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags))
415 	disable_irq_nosync(ab->irq_num[irq_idx]);
424 	struct ath11k_base *ab = irq_grp->ab;
430 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
434 		disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
437 static void __ath11k_pcic_ext_irq_disable(struct ath11k_base *ab)
441 	clear_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags);
444 		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
458 	struct ath11k_base *ab = irq_grp->ab;
464 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
468 		enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
471 void ath11k_pcic_ext_irq_enable(struct ath11k_base *ab)
476 		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
485 	set_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags);
489 static void ath11k_pcic_sync_ext_irqs(struct ath11k_base *ab)
494 		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
498 			synchronize_irq(ab->irq_num[irq_idx]);
503 void ath11k_pcic_ext_irq_disable(struct ath11k_base *ab)
505 	__ath11k_pcic_ext_irq_disable(ab);
506 	ath11k_pcic_sync_ext_irqs(ab);
515 	struct ath11k_base *ab = irq_grp->ab;
519 	work_done = ath11k_dp_service_srng(ab, irq_grp, budget);
523 			enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
535 	struct ath11k_base *ab = irq_grp->ab;
538 	if (!test_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))
541 	ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq %d\n", irq);
547 		disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
555 ath11k_pcic_get_msi_irq(struct ath11k_base *ab, unsigned int vector)
557 	return ab->pci.ops->get_msi_irq(ab, vector);
560 static int ath11k_pcic_ext_irq_config(struct ath11k_base *ab)
566 	ret = ath11k_pcic_get_user_msi_assignment(ab, "DP", &num_vectors,
573 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
577 		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
580 		irq_grp->ab = ab;
589 		if (ab->hw_params.ring_mask->tx[i] ||
590 		    ab->hw_params.ring_mask->rx[i] ||
591 		    ab->hw_params.ring_mask->rx_err[i] ||
592 		    ab->hw_params.ring_mask->rx_wbm_rel[i] ||
593 		    ab->hw_params.ring_mask->reo_status[i] ||
594 		    ab->hw_params.ring_mask->rxdma2host[i] ||
595 		    ab->hw_params.ring_mask->host2rxdma[i] ||
596 		    ab->hw_params.ring_mask->rx_mon_status[i]) {
606 			int irq = ath11k_pcic_get_msi_irq(ab, vector);
610 					irq_grp = &ab->ext_irq_grp[n];
616 			ab->irq_num[irq_idx] = irq;
618 			ath11k_dbg(ab, ATH11K_DBG_PCI,
625 				ath11k_err(ab, "failed request irq %d: %d\n",
628 					irq_grp = &ab->ext_irq_grp[n];
640 int ath11k_pcic_config_irq(struct ath11k_base *ab)
650 	ret = ath11k_pcic_get_user_msi_assignment(ab, "CE", &msi_data_count,
656 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
660 	for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
661 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
665 		irq = ath11k_pcic_get_msi_irq(ab, msi_data);
669 		ce_pipe = &ab->ce.ce_pipe[i];
678 			ath11k_err(ab, "failed to request irq %d: %d\n",
683 		ab->irq_num[irq_idx] = irq;
686 		ath11k_pcic_ce_irq_disable(ab, i);
689 	ret = ath11k_pcic_ext_irq_config(ab);
697 void ath11k_pcic_ce_irqs_enable(struct ath11k_base *ab)
701 	set_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
703 	for (i = 0; i < ab->hw_params.ce_count; i++) {
704 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
706 		ath11k_pcic_ce_irq_enable(ab, i);
711 static void ath11k_pcic_kill_tasklets(struct ath11k_base *ab)
715 	for (i = 0; i < ab->hw_params.ce_count; i++) {
716 		struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
718 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
725 void ath11k_pcic_ce_irq_disable_sync(struct ath11k_base *ab)
727 	ath11k_pcic_ce_irqs_disable(ab);
728 	ath11k_pcic_sync_ce_irqs(ab);
729 	ath11k_pcic_kill_tasklets(ab);
733 void ath11k_pcic_stop(struct ath11k_base *ab)
735 	ath11k_pcic_ce_irq_disable_sync(ab);
736 	ath11k_ce_cleanup_pipes(ab);
740 int ath11k_pcic_start(struct ath11k_base *ab)
742 	set_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
744 	ath11k_pcic_ce_irqs_enable(ab);
745 	ath11k_ce_rx_post_buf(ab);
751 int ath11k_pcic_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
758 	for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) {
759 		entry = &ab->hw_params.svc_to_ce_map[i];
795 int ath11k_pcic_register_pci_ops(struct ath11k_base *ab,
806 	ab->pci.ops = pci_ops;
811 void ath11k_pci_enable_ce_irqs_except_wake_irq(struct ath11k_base *ab)
815 	for (i = 0; i < ab->hw_params.ce_count; i++) {
816 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR ||
819 		ath11k_pcic_ce_irq_enable(ab, i);
824 void ath11k_pci_disable_ce_irqs_except_wake_irq(struct ath11k_base *ab)
830 	for (i = 0; i < ab->hw_params.ce_count; i++) {
831 		ce_pipe = &ab->ce.ce_pipe[i];
834 		if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR ||
838 		disable_irq_nosync(ab->irq_num[irq_idx]);
839 		synchronize_irq(ab->irq_num[irq_idx]);