Lines Matching defs:ab
16 static void ath11k_dp_htt_htc_tx_complete(struct ath11k_base *ab,
24 struct ath11k_base *ab = ar->ab;
29 spin_lock_bh(&ab->base_lock);
30 peer = ath11k_peer_find(ab, vdev_id, addr);
32 ath11k_warn(ab, "failed to lookup peer %pM on vdev %d\n",
34 spin_unlock_bh(&ab->base_lock);
41 spin_unlock_bh(&ab->base_lock);
46 struct ath11k_base *ab = ar->ab;
58 ath11k_warn(ab, "failed to set default routing %d peer :%pM vdev_id :%d\n",
67 ath11k_warn(ab, "failed to setup rxd tid queue for tid %d: %d\n",
75 ath11k_warn(ab, "failed to setup rx defrag context\n");
85 spin_lock_bh(&ab->base_lock);
87 peer = ath11k_peer_find(ab, vdev_id, addr);
89 ath11k_warn(ab, "failed to find the peer to del rx tid\n");
90 spin_unlock_bh(&ab->base_lock);
97 spin_unlock_bh(&ab->base_lock);
102 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring)
108 dma_unmap_single(ab->dev, ring->paddr_unaligned, ring->size,
112 dma_free_coherent(ab->dev, ring->size, ring->vaddr_unaligned,
133 static int ath11k_dp_srng_calculate_msi_group(struct ath11k_base *ab,
141 grp_mask = &ab->hw_params.ring_mask->rx_wbm_rel[0];
144 grp_mask = &ab->hw_params.ring_mask->tx[0];
148 grp_mask = &ab->hw_params.ring_mask->rx_err[0];
151 grp_mask = &ab->hw_params.ring_mask->rx[0];
154 grp_mask = &ab->hw_params.ring_mask->reo_status[0];
158 grp_mask = &ab->hw_params.ring_mask->rx_mon_status[0];
161 grp_mask = &ab->hw_params.ring_mask->rxdma2host[0];
164 grp_mask = &ab->hw_params.ring_mask->host2rxdma[0];
184 static void ath11k_dp_srng_msi_setup(struct ath11k_base *ab,
192 ret = ath11k_get_user_msi_vector(ab, "DP",
198 msi_group_number = ath11k_dp_srng_calculate_msi_group(ab, type,
201 ath11k_dbg(ab, ATH11K_DBG_PCI,
210 ath11k_dbg(ab, ATH11K_DBG_PCI,
215 ath11k_get_msi_address(ab, &addr_lo, &addr_hi);
224 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring,
229 int entry_sz = ath11k_hal_srng_get_entrysize(ab, type);
230 int max_entries = ath11k_hal_srng_get_max_entries(ab, type);
242 if (ab->hw_params.alloc_cacheable_memory) {
258 ring->paddr_unaligned = dma_map_single(ab->dev,
262 if (dma_mapping_error(ab->dev, ring->paddr_unaligned)) {
271 ring->vaddr_unaligned = dma_alloc_coherent(ab->dev, ring->size,
285 ath11k_dp_srng_msi_setup(ab, ¶ms, type, ring_num + mac_id);
330 ath11k_warn(ab, "Not a valid ring type in dp :%d\n", type);
339 ret = ath11k_hal_srng_setup(ab, type, ring_num, mac_id, ¶ms);
341 ath11k_warn(ab, "failed to setup srng: %d ring_id %d\n",
351 void ath11k_dp_stop_shadow_timers(struct ath11k_base *ab)
355 if (!ab->hw_params.supports_shadow_regs)
358 for (i = 0; i < ab->hw_params.max_tx_ring; i++)
359 ath11k_dp_shadow_stop_timer(ab, &ab->dp.tx_ring_timer[i]);
361 ath11k_dp_shadow_stop_timer(ab, &ab->dp.reo_cmd_timer);
364 static void ath11k_dp_srng_common_cleanup(struct ath11k_base *ab)
366 struct ath11k_dp *dp = &ab->dp;
369 ath11k_dp_stop_shadow_timers(ab);
370 ath11k_dp_srng_cleanup(ab, &dp->wbm_desc_rel_ring);
371 ath11k_dp_srng_cleanup(ab, &dp->tcl_cmd_ring);
372 ath11k_dp_srng_cleanup(ab, &dp->tcl_status_ring);
373 for (i = 0; i < ab->hw_params.max_tx_ring; i++) {
374 ath11k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_data_ring);
375 ath11k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_comp_ring);
377 ath11k_dp_srng_cleanup(ab, &dp->reo_reinject_ring);
378 ath11k_dp_srng_cleanup(ab, &dp->rx_rel_ring);
379 ath11k_dp_srng_cleanup(ab, &dp->reo_except_ring);
380 ath11k_dp_srng_cleanup(ab, &dp->reo_cmd_ring);
381 ath11k_dp_srng_cleanup(ab, &dp->reo_status_ring);
384 static int ath11k_dp_srng_common_setup(struct ath11k_base *ab)
386 struct ath11k_dp *dp = &ab->dp;
391 ret = ath11k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring,
395 ath11k_warn(ab, "failed to set up wbm2sw_release ring :%d\n",
400 ret = ath11k_dp_srng_setup(ab, &dp->tcl_cmd_ring, HAL_TCL_CMD, 0, 0,
403 ath11k_warn(ab, "failed to set up tcl_cmd ring :%d\n", ret);
407 ret = ath11k_dp_srng_setup(ab, &dp->tcl_status_ring, HAL_TCL_STATUS,
410 ath11k_warn(ab, "failed to set up tcl_status ring :%d\n", ret);
414 for (i = 0; i < ab->hw_params.max_tx_ring; i++) {
415 tcl_num = ab->hw_params.hal_params->tcl2wbm_rbm_map[i].tcl_ring_num;
416 wbm_num = ab->hw_params.hal_params->tcl2wbm_rbm_map[i].wbm_ring_num;
418 ret = ath11k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_data_ring,
420 ab->hw_params.tx_ring_size);
422 ath11k_warn(ab, "failed to set up tcl_data ring (%d) :%d\n",
427 ret = ath11k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_comp_ring,
431 ath11k_warn(ab, "failed to set up tcl_comp ring (%d) :%d\n",
436 srng = &ab->hal.srng_list[dp->tx_ring[i].tcl_data_ring.ring_id];
437 ath11k_hal_tx_init_data_ring(ab, srng);
439 ath11k_dp_shadow_init_timer(ab, &dp->tx_ring_timer[i],
444 ret = ath11k_dp_srng_setup(ab, &dp->reo_reinject_ring, HAL_REO_REINJECT,
447 ath11k_warn(ab, "failed to set up reo_reinject ring :%d\n",
452 ret = ath11k_dp_srng_setup(ab, &dp->rx_rel_ring, HAL_WBM2SW_RELEASE,
455 ath11k_warn(ab, "failed to set up rx_rel ring :%d\n", ret);
459 ret = ath11k_dp_srng_setup(ab, &dp->reo_except_ring, HAL_REO_EXCEPTION,
462 ath11k_warn(ab, "failed to set up reo_exception ring :%d\n",
467 ret = ath11k_dp_srng_setup(ab, &dp->reo_cmd_ring, HAL_REO_CMD,
470 ath11k_warn(ab, "failed to set up reo_cmd ring :%d\n", ret);
474 srng = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
475 ath11k_hal_reo_init_cmd_ring(ab, srng);
477 ath11k_dp_shadow_init_timer(ab, &dp->reo_cmd_timer,
481 ret = ath11k_dp_srng_setup(ab, &dp->reo_status_ring, HAL_REO_STATUS,
484 ath11k_warn(ab, "failed to set up reo_status ring :%d\n", ret);
491 ab->hw_params.hw_ops->reo_setup(ab);
496 ath11k_dp_srng_common_cleanup(ab);
501 static void ath11k_dp_scatter_idle_link_desc_cleanup(struct ath11k_base *ab)
503 struct ath11k_dp *dp = &ab->dp;
511 dma_free_coherent(ab->dev, HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX,
517 static int ath11k_dp_scatter_idle_link_desc_setup(struct ath11k_base *ab,
523 struct ath11k_dp *dp = &ab->dp;
537 ath11k_hal_srng_get_entrysize(ab, HAL_WBM_IDLE_LINK);
544 slist[i].vaddr = dma_alloc_coherent(ab->dev,
581 ath11k_hal_setup_link_idle_list(ab, slist, num_scatter_buf,
587 ath11k_dp_scatter_idle_link_desc_cleanup(ab);
593 ath11k_dp_link_desc_bank_free(struct ath11k_base *ab,
600 dma_free_coherent(ab->dev,
609 static int ath11k_dp_link_desc_bank_alloc(struct ath11k_base *ab,
614 struct ath11k_dp *dp = &ab->dp;
624 dma_alloc_coherent(ab->dev, desc_sz,
643 ath11k_dp_link_desc_bank_free(ab, dp->link_desc_banks);
648 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab,
652 ath11k_dp_link_desc_bank_free(ab, desc_bank);
655 ath11k_dp_srng_cleanup(ab, ring);
656 ath11k_dp_scatter_idle_link_desc_cleanup(ab);
660 static int ath11k_wbm_idle_ring_setup(struct ath11k_base *ab, u32 *n_link_desc)
662 struct ath11k_dp *dp = &ab->dp;
687 ret = ath11k_dp_srng_setup(ab, &dp->wbm_idle_ring,
690 ath11k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret);
696 int ath11k_dp_link_desc_setup(struct ath11k_base *ab,
729 ret = ath11k_dp_link_desc_bank_alloc(ab, link_desc_banks,
735 entry_sz = ath11k_hal_srng_get_entrysize(ab, ring_type);
741 ret = ath11k_dp_scatter_idle_link_desc_setup(ab, tot_mem_sz,
746 ath11k_warn(ab, "failed to setup scatting idle list descriptor :%d\n",
756 ath11k_hal_srng_access_begin(ab, srng);
765 (desc = ath11k_hal_srng_src_get_next_entry(ab, srng))) {
773 ath11k_hal_srng_access_end(ab, srng);
780 ath11k_dp_link_desc_bank_free(ab, link_desc_banks);
785 int ath11k_dp_service_srng(struct ath11k_base *ab,
796 for (i = 0; i < ab->hw_params.max_tx_ring; i++) {
797 if (BIT(ab->hw_params.hal_params->tcl2wbm_rbm_map[i].wbm_ring_num) &
798 ab->hw_params.ring_mask->tx[grp_id])
799 ath11k_dp_tx_completion_handler(ab, i);
802 if (ab->hw_params.ring_mask->rx_err[grp_id]) {
803 work_done = ath11k_dp_process_rx_err(ab, napi, budget);
810 if (ab->hw_params.ring_mask->rx_wbm_rel[grp_id]) {
811 work_done = ath11k_dp_rx_process_wbm_err(ab,
821 if (ab->hw_params.ring_mask->rx[grp_id]) {
822 i = fls(ab->hw_params.ring_mask->rx[grp_id]) - 1;
823 work_done = ath11k_dp_process_rx(ab, i, napi,
831 if (ab->hw_params.ring_mask->rx_mon_status[grp_id]) {
832 for (i = 0; i < ab->num_radios; i++) {
833 for (j = 0; j < ab->hw_params.num_rxmda_per_pdev; j++) {
834 int id = i * ab->hw_params.num_rxmda_per_pdev + j;
836 if (ab->hw_params.ring_mask->rx_mon_status[grp_id] &
839 ath11k_dp_rx_process_mon_rings(ab,
852 if (ab->hw_params.ring_mask->reo_status[grp_id])
853 ath11k_dp_process_reo_status(ab);
855 for (i = 0; i < ab->num_radios; i++) {
856 for (j = 0; j < ab->hw_params.num_rxmda_per_pdev; j++) {
857 int id = i * ab->hw_params.num_rxmda_per_pdev + j;
859 if (ab->hw_params.ring_mask->rxdma2host[grp_id] & BIT(id)) {
860 work_done = ath11k_dp_process_rxdma_err(ab, id, budget);
868 if (ab->hw_params.ring_mask->host2rxdma[grp_id] & BIT(id)) {
869 struct ath11k *ar = ath11k_ab_to_ar(ab, id);
873 hal_params = ab->hw_params.hal_params;
874 ath11k_dp_rxbufs_replenish(ab, id, rx_ring, 0,
886 void ath11k_dp_pdev_free(struct ath11k_base *ab)
891 del_timer_sync(&ab->mon_reap_timer);
893 for (i = 0; i < ab->num_radios; i++) {
894 ar = ab->pdevs[i].ar;
895 ath11k_dp_rx_pdev_free(ab, i);
901 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab)
908 for (i = 0; i < ab->num_radios; i++) {
909 ar = ab->pdevs[i].ar;
916 for (j = 0; j < ab->hw_params.num_rxmda_per_pdev; j++) {
925 int ath11k_dp_pdev_alloc(struct ath11k_base *ab)
932 for (i = 0; i < ab->num_radios; i++) {
933 ar = ab->pdevs[i].ar;
934 ret = ath11k_dp_rx_pdev_alloc(ab, i);
936 ath11k_warn(ab, "failed to allocate pdev rx for pdev_id :%d\n",
942 ath11k_warn(ab, "failed to initialize mon pdev %d\n",
951 ath11k_dp_pdev_free(ab);
971 status = ath11k_htc_connect_service(&dp->ab->htc, &conn_req,
991 if (arvif->ar->ab->hw_params.htt_peer_map_v2) {
1026 struct ath11k_base *ab = ctx;
1029 dma_unmap_single(ab->dev, ATH11K_SKB_CB(msdu)->paddr, msdu->len,
1037 void ath11k_dp_free(struct ath11k_base *ab)
1039 struct ath11k_dp *dp = &ab->dp;
1042 ath11k_dp_link_desc_cleanup(ab, dp->link_desc_banks,
1045 ath11k_dp_srng_common_cleanup(ab);
1047 ath11k_dp_reo_cmd_list_cleanup(ab);
1049 for (i = 0; i < ab->hw_params.max_tx_ring; i++) {
1052 ath11k_dp_tx_pending_cleanup, ab);
1061 int ath11k_dp_alloc(struct ath11k_base *ab)
1063 struct ath11k_dp *dp = &ab->dp;
1070 dp->ab = ab;
1079 ret = ath11k_wbm_idle_ring_setup(ab, &n_link_desc);
1081 ath11k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret);
1085 srng = &ab->hal.srng_list[dp->wbm_idle_ring.ring_id];
1087 ret = ath11k_dp_link_desc_setup(ab, dp->link_desc_banks,
1090 ath11k_warn(ab, "failed to setup link desc: %d\n", ret);
1094 ret = ath11k_dp_srng_common_setup(ab);
1100 for (i = 0; i < ab->hw_params.max_tx_ring; i++) {
1115 ath11k_hal_tx_set_dscp_tid_map(ab, i);
1122 ath11k_dp_srng_common_cleanup(ab);
1125 ath11k_dp_link_desc_cleanup(ab, dp->link_desc_banks,
1135 struct ath11k_base *ab = update_timer->ab;
1136 struct hal_srng *srng = &ab->hal.srng_list[update_timer->ring_id];
1151 ath11k_hal_srng_shadow_update_hp_tp(ab, srng);
1157 void ath11k_dp_shadow_start_timer(struct ath11k_base *ab,
1163 if (!ab->hw_params.supports_shadow_regs)
1177 void ath11k_dp_shadow_stop_timer(struct ath11k_base *ab,
1180 if (!ab->hw_params.supports_shadow_regs)
1189 void ath11k_dp_shadow_init_timer(struct ath11k_base *ab,
1193 if (!ab->hw_params.supports_shadow_regs)
1198 update_timer->ab = ab;