Lines Matching refs:u32
149 DECLARE_FLEX_ARRAY(u32, data);
156 u32 mac_id__word;
157 u32 hw_queued;
158 u32 hw_reaped;
159 u32 underrun;
160 u32 hw_paused;
161 u32 hw_flush;
162 u32 hw_filt;
163 u32 tx_abort;
164 u32 mpdu_requeued;
165 u32 tx_xretry;
166 u32 data_rc;
167 u32 mpdu_dropped_xretry;
168 u32 illgl_rate_phy_err;
169 u32 cont_xretry;
170 u32 tx_timeout;
171 u32 pdev_resets;
172 u32 phy_underrun;
173 u32 txop_ovf;
174 u32 seq_posted;
175 u32 seq_failed_queueing;
176 u32 seq_completed;
177 u32 seq_restarted;
178 u32 mu_seq_posted;
179 u32 seq_switch_hw_paused;
180 u32 next_seq_posted_dsr;
181 u32 seq_posted_isr;
182 u32 seq_ctrl_cached;
183 u32 mpdu_count_tqm;
184 u32 msdu_count_tqm;
185 u32 mpdu_removed_tqm;
186 u32 msdu_removed_tqm;
187 u32 mpdus_sw_flush;
188 u32 mpdus_hw_filter;
189 u32 mpdus_truncated;
190 u32 mpdus_ack_failed;
191 u32 mpdus_expired;
192 u32 mpdus_seq_hw_retry;
193 u32 ack_tlv_proc;
194 u32 coex_abort_mpdu_cnt_valid;
195 u32 coex_abort_mpdu_cnt;
196 u32 num_total_ppdus_tried_ota;
197 u32 num_data_ppdus_tried_ota;
198 u32 local_ctrl_mgmt_enqued;
199 u32 local_ctrl_mgmt_freed;
200 u32 local_data_enqued;
201 u32 local_data_freed;
202 u32 mpdu_tried;
203 u32 isr_wait_seq_posted;
205 u32 tx_active_dur_us_low;
206 u32 tx_active_dur_us_high;
212 DECLARE_FLEX_ARRAY(u32, urrn_stats);
218 DECLARE_FLEX_ARRAY(u32, flush_errs);
224 DECLARE_FLEX_ARRAY(u32, sifs_status);
230 DECLARE_FLEX_ARRAY(u32, phy_errs);
236 DECLARE_FLEX_ARRAY(u32, sifs_hist_status);
240 u32 num_data_ppdus_legacy_su;
241 u32 num_data_ppdus_ac_su;
242 u32 num_data_ppdus_ax_su;
243 u32 num_data_ppdus_ac_su_txbf;
244 u32 num_data_ppdus_ax_su_txbf;
260 u32 hist_bin_size;
261 u32 tried_mpdu_cnt_hist[]; /* HTT_TX_PDEV_TRIED_MPDU_CNT_HIST */
271 u32 mask;
272 u32 count;
279 u32 count;
283 u32 mac_id__word; /* BIT [ 7 : 0] : mac_id */
284 u32 tx_abort;
285 u32 tx_abort_fail_count;
286 u32 rx_abort;
287 u32 rx_abort_fail_count;
288 u32 warm_reset;
289 u32 cold_reset;
290 u32 tx_flush;
291 u32 tx_glb_reset;
292 u32 tx_txq_reset;
293 u32 rx_timeout_reset;
297 u32 mac_id__word;
298 u32 last_unpause_ppdu_id;
299 u32 hwsch_unpause_wait_tqm_write;
300 u32 hwsch_dummy_tlv_skipped;
301 u32 hwsch_misaligned_offset_received;
302 u32 hwsch_reset_count;
303 u32 hwsch_dev_reset_war;
304 u32 hwsch_delayed_pause;
305 u32 hwsch_long_delayed_pause;
306 u32 sch_rx_ppdu_no_response;
307 u32 sch_selfgen_response;
308 u32 sch_rx_sifs_resp_trigger;
317 u32 last_update_timestamp;
318 u32 last_add_timestamp;
319 u32 last_remove_timestamp;
320 u32 total_processed_msdu_count;
321 u32 cur_msdu_count_in_flowq;
322 u32 sw_peer_id;
323 u32 tx_flow_no__tid_num__drop_rule;
324 u32 last_cycle_enqueue_count;
325 u32 last_cycle_dequeue_count;
326 u32 last_cycle_drop_count;
327 u32 current_drop_th;
341 u32 sw_peer_id__tid_num;
342 u32 num_sched_pending__num_ppdu_in_hwq;
343 u32 tid_flags;
344 u32 hw_queued;
345 u32 hw_reaped;
346 u32 mpdus_hw_filter;
348 u32 qdepth_bytes;
349 u32 qdepth_num_msdu;
350 u32 qdepth_num_mpdu;
351 u32 last_scheduled_tsmp;
352 u32 pause_module_id;
353 u32 block_module_id;
354 u32 tid_tx_airtime;
366 u32 sw_peer_id__tid_num;
367 u32 num_sched_pending__num_ppdu_in_hwq;
368 u32 tid_flags;
369 u32 max_qdepth_bytes;
370 u32 max_qdepth_n_msdus;
371 u32 rsvd;
373 u32 qdepth_bytes;
374 u32 qdepth_num_msdu;
375 u32 qdepth_num_mpdu;
376 u32 last_scheduled_tsmp;
377 u32 pause_module_id;
378 u32 block_module_id;
379 u32 tid_tx_airtime;
380 u32 allow_n_flags;
381 u32 sendn_frms_allowed;
388 u32 sw_peer_id__tid_num;
390 u32 dup_in_reorder;
391 u32 dup_past_outside_window;
392 u32 dup_past_within_window;
393 u32 rxdesc_err_decrypt;
394 u32 tid_rx_airtime;
400 u32 count;
404 u32 ppdu_cnt;
405 u32 mpdu_cnt;
406 u32 msdu_cnt;
407 u32 pause_bitmap;
408 u32 block_bitmap;
409 u32 current_timestamp;
410 u32 peer_tx_airtime;
411 u32 peer_rx_airtime;
413 u32 peer_enqueued_count_low;
414 u32 peer_enqueued_count_high;
415 u32 peer_dequeued_count_low;
416 u32 peer_dequeued_count_high;
417 u32 peer_dropped_count_low;
418 u32 peer_dropped_count_high;
419 u32 ppdu_transmitted_bytes_low;
420 u32 ppdu_transmitted_bytes_high;
421 u32 peer_ttl_removed_count;
422 u32 inactive_time;
430 u32 peer_type;
431 u32 sw_peer_id;
432 u32 vdev_pdev_ast_idx;
434 u32 peer_flags;
435 u32 qpeer_flags;
458 u32 tx_ldpc;
459 u32 rts_cnt;
460 u32 ack_rssi;
462 u32 tx_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
463 u32 tx_su_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
464 u32 tx_mu_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
466 u32 tx_nss[HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS];
468 u32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS];
469 u32 tx_stbc[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
470 u32 tx_pream[HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES];
475 u32 tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
478 u32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS];
490 u32 nsts;
493 u32 rx_ldpc;
495 u32 rts_cnt;
497 u32 rssi_mgmt; /* units = dB above noise floor */
498 u32 rssi_data; /* units = dB above noise floor */
499 u32 rssi_comb; /* units = dB above noise floor */
500 u32 rx_mcs[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS];
502 u32 rx_nss[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS];
503 u32 rx_dcm[HTT_RX_PEER_STATS_NUM_DCM_COUNTERS];
504 u32 rx_stbc[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS];
506 u32 rx_bw[HTT_RX_PEER_STATS_NUM_BW_COUNTERS];
507 u32 rx_pream[HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES];
513 u32 rx_gi[HTT_RX_PEER_STATS_NUM_GI_COUNTERS]
538 u32 mu_mimo_sch_posted;
539 u32 mu_mimo_sch_failed;
540 u32 mu_mimo_ppdu_posted;
544 u32 mu_mimo_mpdus_queued_usr;
545 u32 mu_mimo_mpdus_tried_usr;
546 u32 mu_mimo_mpdus_failed_usr;
547 u32 mu_mimo_mpdus_requeued_usr;
548 u32 mu_mimo_err_no_ba_usr;
549 u32 mu_mimo_mpdu_underrun_usr;
550 u32 mu_mimo_ampdu_underrun_usr;
557 u32 mac_id__hwq_id__word;
562 u32 mac_id__hwq_id__word;
565 u32 xretry;
566 u32 underrun_cnt;
567 u32 flush_cnt;
568 u32 filt_cnt;
569 u32 null_mpdu_bmap;
570 u32 user_ack_failure;
571 u32 ack_tlv_proc;
572 u32 sched_id_proc;
573 u32 null_mpdu_tx_count;
574 u32 mpdu_bmap_not_recvd;
577 u32 num_bar;
578 u32 rts;
579 u32 cts2self;
580 u32 qos_null;
583 u32 mpdu_tried_cnt;
584 u32 mpdu_queued_cnt;
585 u32 mpdu_ack_fail_cnt;
586 u32 mpdu_filt_cnt;
587 u32 false_mpdu_ack_count;
589 u32 txq_timeout;
594 u32 hist_intvl;
596 u32 difs_latency_hist[]; /* HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS */
602 DECLARE_FLEX_ARRAY(u32, cmd_result);
608 DECLARE_FLEX_ARRAY(u32, cmd_stall_status);
614 DECLARE_FLEX_ARRAY(u32, fes_result);
630 u32 hist_bin_size;
632 u32 tried_mpdu_cnt_hist[]; /* HTT_TX_HWQ_TRIED_MPDU_CNT_HIST */
647 DECLARE_FLEX_ARRAY(u32, txop_used_cnt_hist);
652 u32 mac_id__word;
653 u32 su_bar;
654 u32 rts;
655 u32 cts2self;
656 u32 qos_null;
657 u32 delayed_bar_1; /* MU user 1 */
658 u32 delayed_bar_2; /* MU user 2 */
659 u32 delayed_bar_3; /* MU user 3 */
660 u32 delayed_bar_4; /* MU user 4 */
661 u32 delayed_bar_5; /* MU user 5 */
662 u32 delayed_bar_6; /* MU user 6 */
663 u32 delayed_bar_7; /* MU user 7 */
668 u32 ac_su_ndpa;
669 u32 ac_su_ndp;
670 u32 ac_mu_mimo_ndpa;
671 u32 ac_mu_mimo_ndp;
672 u32 ac_mu_mimo_brpoll_1; /* MU user 1 */
673 u32 ac_mu_mimo_brpoll_2; /* MU user 2 */
674 u32 ac_mu_mimo_brpoll_3; /* MU user 3 */
679 u32 ax_su_ndpa;
680 u32 ax_su_ndp;
681 u32 ax_mu_mimo_ndpa;
682 u32 ax_mu_mimo_ndp;
683 u32 ax_mu_mimo_brpoll_1; /* MU user 1 */
684 u32 ax_mu_mimo_brpoll_2; /* MU user 2 */
685 u32 ax_mu_mimo_brpoll_3; /* MU user 3 */
686 u32 ax_mu_mimo_brpoll_4; /* MU user 4 */
687 u32 ax_mu_mimo_brpoll_5; /* MU user 5 */
688 u32 ax_mu_mimo_brpoll_6; /* MU user 6 */
689 u32 ax_mu_mimo_brpoll_7; /* MU user 7 */
690 u32 ax_basic_trigger;
691 u32 ax_bsr_trigger;
692 u32 ax_mu_bar_trigger;
693 u32 ax_mu_rts_trigger;
694 u32 ax_ulmumimo_trigger;
699 u32 ac_su_ndp_err;
700 u32 ac_su_ndpa_err;
701 u32 ac_mu_mimo_ndpa_err;
702 u32 ac_mu_mimo_ndp_err;
703 u32 ac_mu_mimo_brp1_err;
704 u32 ac_mu_mimo_brp2_err;
705 u32 ac_mu_mimo_brp3_err;
710 u32 ax_su_ndp_err;
711 u32 ax_su_ndpa_err;
712 u32 ax_mu_mimo_ndpa_err;
713 u32 ax_mu_mimo_ndp_err;
714 u32 ax_mu_mimo_brp1_err;
715 u32 ax_mu_mimo_brp2_err;
716 u32 ax_mu_mimo_brp3_err;
717 u32 ax_mu_mimo_brp4_err;
718 u32 ax_mu_mimo_brp5_err;
719 u32 ax_mu_mimo_brp6_err;
720 u32 ax_mu_mimo_brp7_err;
721 u32 ax_basic_trigger_err;
722 u32 ax_bsr_trigger_err;
723 u32 ax_mu_bar_trigger_err;
724 u32 ax_mu_rts_trigger_err;
725 u32 ax_ulmumimo_trigger_err;
736 u32 mu_mimo_sch_posted;
737 u32 mu_mimo_sch_failed;
739 u32 mu_mimo_ppdu_posted;
746 u32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS];
747 u32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS];
748 u32 ax_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
749 u32 ax_ul_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
750 u32 ax_ul_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
751 u32 ax_ul_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
752 u32 ax_ul_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
758 u32 ax_ul_mumimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS];
763 u32 ax_ul_mumimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS];
765 u32 ac_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS];
766 u32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS];
770 u32 mu_mimo_mpdus_queued_usr;
771 u32 mu_mimo_mpdus_tried_usr;
772 u32 mu_mimo_mpdus_failed_usr;
773 u32 mu_mimo_mpdus_requeued_usr;
774 u32 mu_mimo_err_no_ba_usr;
775 u32 mu_mimo_mpdu_underrun_usr;
776 u32 mu_mimo_ampdu_underrun_usr;
778 u32 ax_mu_mimo_mpdus_queued_usr;
779 u32 ax_mu_mimo_mpdus_tried_usr;
780 u32 ax_mu_mimo_mpdus_failed_usr;
781 u32 ax_mu_mimo_mpdus_requeued_usr;
782 u32 ax_mu_mimo_err_no_ba_usr;
783 u32 ax_mu_mimo_mpdu_underrun_usr;
784 u32 ax_mu_mimo_ampdu_underrun_usr;
786 u32 ax_ofdma_mpdus_queued_usr;
787 u32 ax_ofdma_mpdus_tried_usr;
788 u32 ax_ofdma_mpdus_failed_usr;
789 u32 ax_ofdma_mpdus_requeued_usr;
790 u32 ax_ofdma_err_no_ba_usr;
791 u32 ax_ofdma_mpdu_underrun_usr;
792 u32 ax_ofdma_ampdu_underrun_usr;
801 u32 mpdus_queued_usr;
802 u32 mpdus_tried_usr;
803 u32 mpdus_failed_usr;
804 u32 mpdus_requeued_usr;
805 u32 err_no_ba_usr;
806 u32 mpdu_underrun_usr;
807 u32 ampdu_underrun_usr;
808 u32 user_index;
809 u32 tx_sched_mode; /* HTT_STATS_TX_SCHED_MODE_xxx */
816 DECLARE_FLEX_ARRAY(u32, sched_cmd_posted);
822 DECLARE_FLEX_ARRAY(u32, sched_cmd_reaped);
828 DECLARE_FLEX_ARRAY(u32, sched_order_su);
856 DECLARE_FLEX_ARRAY(u32, sched_ineligibility);
863 u32 mac_id__txq_id__word;
864 u32 sched_policy;
865 u32 last_sched_cmd_posted_timestamp;
866 u32 last_sched_cmd_compl_timestamp;
867 u32 sched_2_tac_lwm_count;
868 u32 sched_2_tac_ring_full;
869 u32 sched_cmd_post_failure;
870 u32 num_active_tids;
871 u32 num_ps_schedules;
872 u32 sched_cmds_pending;
873 u32 num_tid_register;
874 u32 num_tid_unregister;
875 u32 num_qstats_queried;
876 u32 qstats_update_pending;
877 u32 last_qstats_query_timestamp;
878 u32 num_tqm_cmdq_full;
879 u32 num_de_sched_algo_trigger;
880 u32 num_rt_sched_algo_trigger;
881 u32 num_tqm_sched_algo_trigger;
882 u32 notify_sched;
883 u32 dur_based_sendn_term;
890 u32 mac_id__word;
892 u32 current_timestamp;
903 DECLARE_FLEX_ARRAY(u32, gen_mpdu_end_reason);
909 DECLARE_FLEX_ARRAY(u32, list_mpdu_end_reason);
915 DECLARE_FLEX_ARRAY(u32, list_mpdu_cnt_hist);
919 u32 msdu_count;
920 u32 mpdu_count;
921 u32 remove_msdu;
922 u32 remove_mpdu;
923 u32 remove_msdu_ttl;
924 u32 send_bar;
925 u32 bar_sync;
926 u32 notify_mpdu;
927 u32 sync_cmd;
928 u32 write_cmd;
929 u32 hwsch_trigger;
930 u32 ack_tlv_proc;
931 u32 gen_mpdu_cmd;
932 u32 gen_list_cmd;
933 u32 remove_mpdu_cmd;
934 u32 remove_mpdu_tried_cmd;
935 u32 mpdu_queue_stats_cmd;
936 u32 mpdu_head_info_cmd;
937 u32 msdu_flow_stats_cmd;
938 u32 remove_msdu_cmd;
939 u32 remove_msdu_ttl_cmd;
940 u32 flush_cache_cmd;
941 u32 update_mpduq_cmd;
942 u32 enqueue;
943 u32 enqueue_notify;
944 u32 notify_mpdu_at_head;
945 u32 notify_mpdu_state_valid;
958 u32 sched_udp_notify1;
959 u32 sched_udp_notify2;
960 u32 sched_nonudp_notify1;
961 u32 sched_nonudp_notify2;
965 u32 mac_id__word;
966 u32 max_cmdq_id;
967 u32 list_mpdu_cnt_hist_intvl;
970 u32 add_msdu;
971 u32 q_empty;
972 u32 q_not_empty;
973 u32 drop_notification;
974 u32 desc_threshold;
979 u32 q_empty_failure;
980 u32 q_not_empty_failure;
981 u32 add_msdu_failure;
989 u32 mac_id__cmdq_id__word;
990 u32 sync_cmd;
991 u32 write_cmd;
992 u32 gen_mpdu_cmd;
993 u32 mpdu_queue_stats_cmd;
994 u32 mpdu_head_info_cmd;
995 u32 msdu_flow_stats_cmd;
996 u32 remove_mpdu_cmd;
997 u32 remove_msdu_cmd;
998 u32 flush_cache_cmd;
999 u32 update_mpduq_cmd;
1000 u32 update_msduq_cmd;
1006 u32 m1_packets;
1007 u32 m2_packets;
1008 u32 m3_packets;
1009 u32 m4_packets;
1010 u32 g1_packets;
1011 u32 g2_packets;
1015 u32 ap_bss_peer_not_found;
1016 u32 ap_bcast_mcast_no_peer;
1017 u32 sta_delete_in_progress;
1018 u32 ibss_no_bss_peer;
1019 u32 invalid_vdev_type;
1020 u32 invalid_ast_peer_entry;
1021 u32 peer_entry_invalid;
1022 u32 ethertype_not_ip;
1023 u32 eapol_lookup_failed;
1024 u32 qpeer_not_allow_data;
1025 u32 fse_tid_override;
1026 u32 ipv6_jumbogram_zero_length;
1027 u32 qos_to_non_qos_in_prog;
1031 u32 arp_packets;
1032 u32 igmp_packets;
1033 u32 dhcp_packets;
1034 u32 host_inspected;
1035 u32 htt_included;
1036 u32 htt_valid_mcs;
1037 u32 htt_valid_nss;
1038 u32 htt_valid_preamble_type;
1039 u32 htt_valid_chainmask;
1040 u32 htt_valid_guard_interval;
1041 u32 htt_valid_retries;
1042 u32 htt_valid_bw_info;
1043 u32 htt_valid_power;
1044 u32 htt_valid_key_flags;
1045 u32 htt_valid_no_encryption;
1046 u32 fse_entry_count;
1047 u32 fse_priority_be;
1048 u32 fse_priority_high;
1049 u32 fse_priority_low;
1050 u32 fse_traffic_ptrn_be;
1051 u32 fse_traffic_ptrn_over_sub;
1052 u32 fse_traffic_ptrn_bursty;
1053 u32 fse_traffic_ptrn_interactive;
1054 u32 fse_traffic_ptrn_periodic;
1055 u32 fse_hwqueue_alloc;
1056 u32 fse_hwqueue_created;
1057 u32 fse_hwqueue_send_to_host;
1058 u32 mcast_entry;
1059 u32 bcast_entry;
1060 u32 htt_update_peer_cache;
1061 u32 htt_learning_frame;
1062 u32 fse_invalid_peer;
1068 u32 mec_notify;
1072 u32 eok;
1073 u32 classify_done;
1074 u32 lookup_failed;
1075 u32 send_host_dhcp;
1076 u32 send_host_mcast;
1077 u32 send_host_unknown_dest;
1078 u32 send_host;
1079 u32 status_invalid;
1083 u32 enqueued_pkts;
1084 u32 to_tqm;
1085 u32 to_tqm_bypass;
1089 u32 discarded_pkts;
1090 u32 local_frames;
1091 u32 is_ext_msdu;
1095 u32 tcl_dummy_frame;
1096 u32 tqm_dummy_frame;
1097 u32 tqm_notify_frame;
1098 u32 fw2wbm_enq;
1099 u32 tqm_bypass_frame;
1114 DECLARE_FLEX_ARRAY(u32, fw2wbm_ring_full_hist);
1118 u32 mac_id__word;
1121 u32 tcl2fw_entry_count;
1122 u32 not_to_fw;
1123 u32 invalid_pdev_vdev_peer;
1124 u32 tcl_res_invalid_addrx;
1125 u32 wbm2fw_entry_count;
1126 u32 invalid_pdev;
1143 u32 base_addr; /* DWORD aligned base memory address of the ring */
1144 u32 elem_size;
1145 u32 num_elems__prefetch_tail_idx;
1146 u32 head_idx__tail_idx;
1147 u32 shadow_head_idx__shadow_tail_idx;
1148 u32 num_tail_incr;
1149 u32 lwm_thresh__hwm_thresh;
1150 u32 overrun_hit_count;
1151 u32 underrun_hit_count;
1152 u32 prod_blockwait_count;
1153 u32 cons_blockwait_count;
1154 u32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS];
1155 u32 high_wm_hit_count[HTT_STATS_HIGH_WM_BINS];
1159 u32 mac_id__word;
1160 u32 num_records;
1167 DECLARE_FLEX_ARRAY(u32, dwords_used_by_user_n);
1172 u32 client_id;
1174 u32 buf_min;
1176 u32 buf_max;
1178 u32 buf_busy;
1180 u32 buf_alloc;
1182 u32 buf_avail;
1184 u32 num_users;
1188 u32 mac_id__word;
1192 u32 buf_total;
1196 u32 mem_empty;
1198 u32 deallocate_bufs;
1200 u32 num_records;
1218 u32 mac_id__ring_id__arena__ep;
1219 u32 base_addr_lsb; /* DWORD aligned base memory address of the ring */
1220 u32 base_addr_msb;
1221 u32 ring_size;
1222 u32 elem_size;
1224 u32 num_avail_words__num_valid_words;
1225 u32 head_ptr__tail_ptr;
1226 u32 consumer_empty__producer_full;
1227 u32 prefetch_count__internal_tail_ptr;
1231 u32 num_records;
1250 u32 mac_id__word;
1251 u32 tx_ldpc;
1252 u32 rts_cnt;
1254 u32 ack_rssi;
1256 u32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1258 u32 tx_su_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1259 u32 tx_mu_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1262 u32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1264 u32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1265 u32 tx_stbc[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1266 u32 tx_pream[HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES];
1271 u32 tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1274 u32 tx_dcm[HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS];
1276 u32 rts_success;
1288 u32 tx_legacy_cck_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS];
1289 u32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS];
1291 u32 ac_mu_mimo_tx_ldpc;
1292 u32 ax_mu_mimo_tx_ldpc;
1293 u32 ofdma_tx_ldpc;
1302 u32 tx_he_ltf[HTT_TX_PDEV_STATS_NUM_LTF];
1304 u32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1305 u32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1306 u32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1308 u32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1309 u32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1310 u32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1312 u32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1313 u32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1314 u32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1316 u32 ac_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1318 u32 ax_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1320 u32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1339 u32 mac_id__word;
1340 u32 nsts;
1342 u32 rx_ldpc;
1343 u32 rts_cnt;
1345 u32 rssi_mgmt; /* units = dB above noise floor */
1346 u32 rssi_data; /* units = dB above noise floor */
1347 u32 rssi_comb; /* units = dB above noise floor */
1348 u32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1350 u32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1351 u32 rx_dcm[HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS];
1352 u32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1354 u32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
1355 u32 rx_pream[HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES];
1363 u32 rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1366 u32 rx_11ax_su_ext;
1367 u32 rx_11ac_mumimo;
1368 u32 rx_11ax_mumimo;
1369 u32 rx_11ax_ofdma;
1370 u32 txbf;
1371 u32 rx_legacy_cck_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS];
1372 u32 rx_legacy_ofdm_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS];
1373 u32 rx_active_dur_us_low;
1374 u32 rx_active_dur_us_high;
1376 u32 rx_11ax_ul_ofdma;
1378 u32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1379 u32 ul_ofdma_rx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1381 u32 ul_ofdma_rx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1382 u32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1383 u32 ul_ofdma_rx_stbc;
1384 u32 ul_ofdma_rx_ldpc;
1387 u32 rx_ulofdma_non_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */
1388 u32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */
1389 u32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */
1390 u32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */
1392 u32 nss_count;
1393 u32 pilot_count;
1412 u32 per_chain_rssi_pkt_type;
1416 u32 rx_su_ndpa;
1417 u32 rx_11ax_su_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1418 u32 rx_mu_ndpa;
1419 u32 rx_11ax_mu_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1420 u32 rx_br_poll;
1421 u32 rx_11ax_dl_ofdma_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1422 u32 rx_11ax_dl_ofdma_ru[HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS];
1424 u32 rx_ulmumimo_non_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER];
1425 u32 rx_ulmumimo_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER];
1426 u32 rx_ulmumimo_mpdu_ok[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER];
1427 u32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER];
1428 u32 rx_ulofdma_non_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
1429 u32 rx_ulofdma_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
1434 u32 fw_reo_ring_data_msdu;
1435 u32 fw_to_host_data_msdu_bcmc;
1436 u32 fw_to_host_data_msdu_uc;
1437 u32 ofld_remote_data_buf_recycle_cnt;
1438 u32 ofld_remote_free_buf_indication_cnt;
1440 u32 ofld_buf_to_host_data_msdu_uc;
1441 u32 reo_fw_ring_to_host_data_msdu_uc;
1443 u32 wbm_sw_ring_reap;
1444 u32 wbm_forward_to_host_cnt;
1445 u32 wbm_target_recycle_cnt;
1447 u32 target_refill_ring_recycle_cnt;
1453 DECLARE_FLEX_ARRAY(u32, refill_ring_empty_cnt);
1459 DECLARE_FLEX_ARRAY(u32, refill_ring_num_refill);
1491 DECLARE_FLEX_ARRAY(u32, rxdma_err); /* HTT_RX_RXDMA_MAX_ERR_CODE */
1523 DECLARE_FLEX_ARRAY(u32, reo_err); /* HTT_RX_REO_MAX_ERR_CODE */
1530 u32 mac_id__word;
1531 u32 ppdu_recvd;
1532 u32 mpdu_cnt_fcs_ok;
1533 u32 mpdu_cnt_fcs_err;
1534 u32 tcp_msdu_cnt;
1535 u32 tcp_ack_msdu_cnt;
1536 u32 udp_msdu_cnt;
1537 u32 other_msdu_cnt;
1538 u32 fw_ring_mpdu_ind;
1539 u32 fw_ring_mgmt_subtype[HTT_STATS_SUBTYPE_MAX];
1540 u32 fw_ring_ctrl_subtype[HTT_STATS_SUBTYPE_MAX];
1541 u32 fw_ring_mcast_data_msdu;
1542 u32 fw_ring_bcast_data_msdu;
1543 u32 fw_ring_ucast_data_msdu;
1544 u32 fw_ring_null_data_msdu;
1545 u32 fw_ring_mpdu_drop;
1546 u32 ofld_local_data_ind_cnt;
1547 u32 ofld_local_data_buf_recycle_cnt;
1548 u32 drx_local_data_ind_cnt;
1549 u32 drx_local_data_buf_recycle_cnt;
1550 u32 local_nondata_ind_cnt;
1551 u32 local_nondata_buf_recycle_cnt;
1553 u32 fw_status_buf_ring_refill_cnt;
1554 u32 fw_status_buf_ring_empty_cnt;
1555 u32 fw_pkt_buf_ring_refill_cnt;
1556 u32 fw_pkt_buf_ring_empty_cnt;
1557 u32 fw_link_buf_ring_refill_cnt;
1558 u32 fw_link_buf_ring_empty_cnt;
1560 u32 host_pkt_buf_ring_refill_cnt;
1561 u32 host_pkt_buf_ring_empty_cnt;
1562 u32 mon_pkt_buf_ring_refill_cnt;
1563 u32 mon_pkt_buf_ring_empty_cnt;
1564 u32 mon_status_buf_ring_refill_cnt;
1565 u32 mon_status_buf_ring_empty_cnt;
1566 u32 mon_desc_buf_ring_refill_cnt;
1567 u32 mon_desc_buf_ring_empty_cnt;
1568 u32 mon_dest_ring_update_cnt;
1569 u32 mon_dest_ring_full_cnt;
1571 u32 rx_suspend_cnt;
1572 u32 rx_suspend_fail_cnt;
1573 u32 rx_resume_cnt;
1574 u32 rx_resume_fail_cnt;
1575 u32 rx_ring_switch_cnt;
1576 u32 rx_ring_restore_cnt;
1577 u32 rx_flush_cnt;
1578 u32 rx_recovery_reset_cnt;
1584 u32 mac_id__word;
1585 u32 total_phy_err_cnt;
1634 u32 phy_err[HTT_STATS_PHY_ERR_MAX];
1640 DECLARE_FLEX_ARRAY(u32, fw_ring_mpdu_err); /* HTT_RX_STATS_RXDMA_MAX_ERR */
1646 DECLARE_FLEX_ARRAY(u32, fw_mpdu_drop); /* HTT_RX_STATS_FW_DROP_REASON_MAX */
1660 u32 tx_frame_usec;
1661 u32 rx_frame_usec;
1662 u32 rx_clear_usec;
1663 u32 my_rx_frame_usec;
1664 u32 usec_cnt;
1665 u32 med_rx_idle_usec;
1666 u32 med_tx_idle_global_usec;
1667 u32 cca_obss_usec;
1671 u32 chan_num;
1673 u32 num_records;
1674 u32 valid_cca_counters_bitmap;
1675 u32 collection_interval;
1687 u32 vdev_id;
1689 u32 flow_id_flags;
1694 u32 dialog_id;
1695 u32 wake_dura_us;
1696 u32 wake_intvl_us;
1697 u32 sp_offset_us;
1701 u32 pdev_id;
1702 u32 num_sessions;
1727 u32 sample_id;
1728 u32 total_max;
1729 u32 total_avg;
1730 u32 total_sample;
1731 u32 non_zeros_avg;
1732 u32 non_zeros_sample;
1733 u32 last_non_zeros_max;
1734 u32 last_non_zeros_min;
1735 u32 last_non_zeros_avg;
1736 u32 last_non_zeros_sample;
1756 u32 tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */
1758 u32 cbf_20[HTT_TXBF_MAX_NUM_OF_MODES];
1759 u32 cbf_40[HTT_TXBF_MAX_NUM_OF_MODES];
1760 u32 cbf_80[HTT_TXBF_MAX_NUM_OF_MODES];
1761 u32 cbf_160[HTT_TXBF_MAX_NUM_OF_MODES];
1764 * u32. The stats for a particular user/bw combination is
1771 u32 sounding[HTT_TX_NUM_OF_SOUNDING_STATS_WORDS];
1775 u32 num_obss_tx_ppdu_success;
1776 u32 num_obss_tx_ppdu_failure;
1777 u32 num_sr_tx_transmissions;
1778 u32 num_spatial_reuse_opportunities;
1779 u32 num_non_srg_opportunities;
1780 u32 num_non_srg_ppdu_tried;
1781 u32 num_non_srg_ppdu_success;
1782 u32 num_srg_opportunities;
1783 u32 num_srg_ppdu_tried;
1784 u32 num_srg_ppdu_success;
1785 u32 num_psr_opportunities;
1786 u32 num_psr_ppdu_tried;
1787 u32 num_psr_ppdu_success;
1791 u32 pdev_id;
1792 u32 current_head_idx;
1793 u32 current_tail_idx;
1794 u32 num_htt_msgs_sent;
1798 u32 backpressure_time_ms;
1812 u32 backpressure_hist[5];
1821 u32 tx_su_txbf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS];
1823 u32 tx_su_ibf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS];
1825 u32 tx_su_ol_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS];
1827 u32 tx_su_txbf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1829 u32 tx_su_ibf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1831 u32 tx_su_ol_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1833 u32 tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
1835 u32 tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
1837 u32 tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
1842 u32 ax_ofdma_ndpa_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1844 u32 ax_ofdma_ndpa_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1846 u32 ax_ofdma_ndpa_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1848 u32 ax_ofdma_ndpa_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1853 u32 ax_ofdma_ndp_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1855 u32 ax_ofdma_ndp_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1857 u32 ax_ofdma_ndp_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1859 u32 ax_ofdma_ndp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1864 u32 ax_ofdma_brpoll_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1866 u32 ax_ofdma_brpoll_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1868 u32 ax_ofdma_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1870 u32 ax_ofdma_brp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1874 u32 ax_ofdma_brp_err_num_cbf_rcvd[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS + 1];
1879 u32 ax_ofdma_num_ppdu_steer[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1881 u32 ax_ofdma_num_ppdu_ol[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1885 u32 ax_ofdma_num_usrs_prefetch[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1887 u32 ax_ofdma_num_usrs_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1889 u32 ax_ofdma_num_usrs_force_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1901 u32 rx_ofdma_timing_err_cnt;
1906 u32 rx_cck_fail_cnt;
1908 u32 mactx_abort_cnt;
1910 u32 macrx_abort_cnt;
1912 u32 phytx_abort_cnt;
1914 u32 phyrx_abort_cnt;
1916 u32 phyrx_defer_abort_cnt;
1918 u32 rx_gain_adj_lstf_event_cnt;
1920 u32 rx_gain_adj_non_legacy_cnt;
1926 u32 rx_pkt_cnt[HTT_MAX_RX_PKT_CNT];
1932 u32 rx_pkt_crc_pass_cnt[HTT_MAX_RX_PKT_CRC_PASS_CNT];
1940 u32 per_blk_err_cnt[HTT_MAX_PER_BLK_ERR_CNT];
1949 u32 rx_ota_err_cnt[HTT_MAX_RX_OTA_ERR_CNT];
1956 u32 false_radar_cnt;
1958 u32 radar_cs_cnt;
1966 u32 fw_run_time;
1970 u32 pdev_id;
1971 u32 cf_active_low_fail_cnt;
1972 u32 cf_active_low_pass_cnt;
1973 u32 phy_off_through_vreg_cnt;
1974 u32 force_calibration_cnt;
1975 u32 rf_mode_switch_phy_off_cnt;
1979 u32 pdev_id;
1980 u32 chan_mhz;
1981 u32 chan_band_center_freq1;
1982 u32 chan_band_center_freq2;
1983 u32 chan_phy_mode;
1984 u32 chan_flags;
1985 u32 chan_num;
1986 u32 reset_cause;
1987 u32 prev_reset_cause;
1988 u32 phy_warm_reset_src;
1989 u32 rx_gain_tbl_mode;
1990 u32 xbar_val;
1991 u32 force_calibration;
1992 u32 phyrf_mode;
1993 u32 phy_homechan;
1994 u32 phy_tx_ch_mask;
1995 u32 phy_rx_ch_mask;
1996 u32 phybb_ini_mask;
1997 u32 phyrf_ini_mask;
1998 u32 phy_dfs_en_mask;
1999 u32 phy_sscan_en_mask;
2000 u32 phy_synth_sel_mask;
2001 u32 phy_adfs_freq;
2002 u32 cck_fir_settings;
2003 u32 phy_dyn_pri_chan;
2004 u32 cca_thresh;
2005 u32 dyn_cca_status;
2006 u32 rxdesense_thresh_hw;
2007 u32 rxdesense_thresh_sw;
2015 u32 peer_tx_mgmt_subtype[ATH11K_STATS_MGMT_FRM_TYPE_MAX];
2017 u32 peer_rx_mgmt_subtype[ATH11K_STATS_MGMT_FRM_TYPE_MAX];