ath/ath11k/ce.c

259 void ath11k_ce_stop_shadow_timers(struct ath11k_base *ab)
263 	if (!ab->hw_params.supports_shadow_regs)
266 	for (i = 0; i < ab->hw_params.ce_count; i++)
268 			ath11k_dp_shadow_stop_timer(ab, &ab->ce.hp_timer[i]);
274 	struct ath11k_base *ab = pipe->ab;
282 	lockdep_assert_held(&ab->ce.ce_lock);
286 	srng = &ab->hal.srng_list[ring->hal_ring_id];
290 	ath11k_hal_srng_access_begin(ab, srng);
292 	if (unlikely(ath11k_hal_srng_src_num_free(ab, srng, false) < 1)) {
297 	desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
313 	ath11k_hal_srng_access_end(ab, srng);
322 	struct ath11k_base *ab = pipe->ab;
330 	spin_lock_bh(&ab->ce.ce_lock);
340 		paddr = dma_map_single(ab->dev, skb->data,
343 		if (unlikely(dma_mapping_error(ab->dev, paddr))) {
344 			ath11k_warn(ab, "failed to dma map ce rx buf\n");
355 			ath11k_warn(ab, "failed to enqueue rx buf: %d\n", ret);
356 			dma_unmap_single(ab->dev, paddr,
365 	spin_unlock_bh(&ab->ce.ce_lock);
372 	struct ath11k_base *ab = pipe->ab;
379 	spin_lock_bh(&ab->ce.ce_lock);
384 	srng = &ab->hal.srng_list[pipe->status_ring->hal_ring_id];
388 	ath11k_hal_srng_access_begin(ab, srng);
390 	desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
410 	ath11k_hal_srng_access_end(ab, srng);
414 	spin_unlock_bh(&ab->ce.ce_lock);
421 	struct ath11k_base *ab = pipe->ab;
430 		dma_unmap_single(ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
434 			ath11k_warn(ab, "rxed more than expected (nbytes %d, max %d)",
445 		ath11k_dbg(ab, ATH11K_DBG_CE, "rx ce pipe %d len %d\n",
447 		pipe->recv_cb(ab, skb);
452 		ath11k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n",
454 		mod_timer(&ab->rx_replenish_retry,
461 	struct ath11k_base *ab = pipe->ab;
468 	spin_lock_bh(&ab->ce.ce_lock);
473 	srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id];
477 	ath11k_hal_srng_access_begin(ab, srng);
479 	desc = ath11k_hal_srng_src_reap_next(ab, srng);
495 	spin_unlock_bh(&ab->ce.ce_lock);
502 	struct ath11k_base *ab = pipe->ab;
511 		dma_unmap_single(ab->dev, ATH11K_SKB_CB(skb)->paddr, skb->len,
514 		if ((!pipe->send_cb) || ab->hw_params.credit_flow) {
523 		ath11k_dbg(ab, ATH11K_DBG_CE, "tx ce pipe %d len %d\n",
525 		pipe->send_cb(ab, skb);
529 static void ath11k_ce_srng_msi_ring_params_setup(struct ath11k_base *ab, u32 ce_id,
539 	ret = ath11k_get_user_msi_vector(ab, "CE",
546 	ath11k_get_msi_address(ab, &addr_lo, &addr_hi);
547 	ath11k_get_ce_msi_idx(ab, ce_id, &msi_data_idx);
555 static int ath11k_ce_init_ring(struct ath11k_base *ab,
566 	if (!(CE_ATTR_DIS_INTR & ab->hw_params.host_ce_config[ce_id].flags))
567 		ath11k_ce_srng_msi_ring_params_setup(ab, ce_id, &params);
571 		if (!(CE_ATTR_DIS_INTR & ab->hw_params.host_ce_config[ce_id].flags))
575 		params.max_buffer_len = ab->hw_params.host_ce_config[ce_id].src_sz_max;
576 		if (!(ab->hw_params.host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) {
583 		if (!(ab->hw_params.host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) {
589 		ath11k_warn(ab, "Invalid CE ring type %d\n", type);
595 	ret = ath11k_hal_srng_setup(ab, type, ce_id, 0, &params);
597 		ath11k_warn(ab, "failed to setup srng: %d ring_id %d\n",
604 	if (ab->hw_params.supports_shadow_regs &&
606 		ath11k_dp_shadow_init_timer(ab, &ab->ce.hp_timer[ce_id],
614 ath11k_ce_alloc_ring(struct ath11k_base *ab, int nentries, int desc_sz)
630 		dma_alloc_coherent(ab->dev,
650 static int ath11k_ce_alloc_pipe(struct ath11k_base *ab, int ce_id)
652 	struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id];
653 	const struct ce_attr *attr = &ab->hw_params.host_ce_config[ce_id];
664 		ring = ath11k_ce_alloc_ring(ab, nentries, desc_sz);
674 		ring = ath11k_ce_alloc_ring(ab, nentries, desc_sz);
680 		ring = ath11k_ce_alloc_ring(ab, nentries, desc_sz);
689 void ath11k_ce_per_engine_service(struct ath11k_base *ab, u16 ce_id)
691 	struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id];
692 	const struct ce_attr *attr = &ab->hw_params.host_ce_config[ce_id];
701 void ath11k_ce_poll_send_completed(struct ath11k_base *ab, u8 pipe_id)
703 	struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id];
704 	const struct ce_attr *attr =  &ab->hw_params.host_ce_config[pipe_id];
711 int ath11k_ce_send(struct ath11k_base *ab, struct sk_buff *skb, u8 pipe_id,
714 	struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id];
728 		spin_lock_bh(&ab->ce.ce_lock);
739 		spin_unlock_bh(&ab->ce.ce_lock);
742 			ath11k_ce_poll_send_completed(ab, pipe->pipe_num);
745 	if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
748 	spin_lock_bh(&ab->ce.ce_lock);
753 	srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id];
757 	ath11k_hal_srng_access_begin(ab, srng);
759 	if (unlikely(ath11k_hal_srng_src_num_free(ab, srng, false) < 1)) {
760 		ath11k_hal_srng_access_end(ab, srng);
765 	desc = ath11k_hal_srng_src_get_next_reaped(ab, srng);
767 		ath11k_hal_srng_access_end(ab, srng);
782 	ath11k_hal_srng_access_end(ab, srng);
785 		ath11k_dp_shadow_start_timer(ab, srng, &ab->ce.hp_timer[pipe_id]);
789 	spin_unlock_bh(&ab->ce.ce_lock);
796 	spin_unlock_bh(&ab->ce.ce_lock);
803 	struct ath11k_base *ab = pipe->ab;
817 		dma_unmap_single(ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
823 static void ath11k_ce_shadow_config(struct ath11k_base *ab)
827 	for (i = 0; i < ab->hw_params.ce_count; i++) {
828 		if (ab->hw_params.host_ce_config[i].src_nentries)
829 			ath11k_hal_srng_update_shadow_config(ab,
832 		if (ab->hw_params.host_ce_config[i].dest_nentries) {
833 			ath11k_hal_srng_update_shadow_config(ab,
836 			ath11k_hal_srng_update_shadow_config(ab,
842 void ath11k_ce_get_shadow_config(struct ath11k_base *ab,
845 	if (!ab->hw_params.supports_shadow_regs)
848 	ath11k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len);
858 	ath11k_hal_srng_shadow_config(ab);
859 	ath11k_ce_shadow_config(ab);
862 	ath11k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len);
866 void ath11k_ce_cleanup_pipes(struct ath11k_base *ab)
871 	ath11k_ce_stop_shadow_timers(ab);
873 	for (pipe_num = 0; pipe_num < ab->hw_params.ce_count; pipe_num++) {
874 		pipe = &ab->ce.ce_pipe[pipe_num];
878 		ath11k_ce_poll_send_completed(ab, pipe_num);
885 void ath11k_ce_rx_post_buf(struct ath11k_base *ab)
891 	for (i = 0; i < ab->hw_params.ce_count; i++) {
892 		pipe = &ab->ce.ce_pipe[i];
898 			ath11k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n",
900 			mod_timer(&ab->rx_replenish_retry,
911 	struct ath11k_base *ab = from_timer(ab, t, rx_replenish_retry);
913 	ath11k_ce_rx_post_buf(ab);
916 int ath11k_ce_init_pipes(struct ath11k_base *ab)
922 	for (i = 0; i < ab->hw_params.ce_count; i++) {
923 		pipe = &ab->ce.ce_pipe[i];
926 			ret = ath11k_ce_init_ring(ab, pipe->src_ring, i,
929 				ath11k_warn(ab, "failed to init src ring: %d\n",
940 			ret = ath11k_ce_init_ring(ab, pipe->dest_ring, i,
943 				ath11k_warn(ab, "failed to init dest ring: %d\n",
957 			ret = ath11k_ce_init_ring(ab, pipe->status_ring, i,
960 				ath11k_warn(ab, "failed to init dest status ing: %d\n",
974 void ath11k_ce_free_pipes(struct ath11k_base *ab)
981 	for (i = 0; i < ab->hw_params.ce_count; i++) {
982 		pipe = &ab->ce.ce_pipe[i];
985 			ath11k_dp_shadow_stop_timer(ab, &ab->ce.hp_timer[i]);
990 			dma_free_coherent(ab->dev,
1002 			dma_free_coherent(ab->dev,
1015 			dma_free_coherent(ab->dev,
1027 int ath11k_ce_alloc_pipes(struct ath11k_base *ab)
1034 	spin_lock_init(&ab->ce.ce_lock);
1036 	for (i = 0; i < ab->hw_params.ce_count; i++) {
1037 		attr = &ab->hw_params.host_ce_config[i];
1038 		pipe = &ab->ce.ce_pipe[i];
1040 		pipe->ab = ab;
1043 		ret = ath11k_ce_alloc_pipe(ab, i);
1046 			ath11k_ce_free_pipes(ab);
1074 int ath11k_ce_get_attr_flags(struct ath11k_base *ab, int ce_id)
1076 	if (ce_id >= ab->hw_params.ce_count)
1079 	return ab->hw_params.host_ce_config[ce_id].flags;