ath/ath10k/snoc.c

476 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
478 	iowrite32(value, ar_snoc->mem + offset);
483 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
486 	val = ioread32(ar_snoc->mem + offset);
534 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
553 			mod_timer(&ar_snoc->rx_post_retry, jiffies +
562 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
566 		ath10k_snoc_rx_post_pipe(&ar_snoc->pipe_info[i]);
574 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
575 	struct ath10k_snoc_pipe *pipe_info =  &ar_snoc->pipe_info[ce_state->id];
647 	struct ath10k_snoc *ar_snoc = from_timer(ar_snoc, t, rx_post_retry);
648 	struct ath10k *ar = ar_snoc->ar;
689 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
695 	snoc_pipe = &ar_snoc->pipe_info[pipe_id];
750 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
754 	return ath10k_ce_num_free_src_entries(ar_snoc->pipe_info[pipe].ce_hdl);
831 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
835 		disable_irq(ar_snoc->ce_irqs[id].irq_line);
840 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
844 		enable_irq(ar_snoc->ce_irqs[id].irq_line);
910 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
914 	del_timer_sync(&ar_snoc->rx_post_retry);
916 		pipe_info = &ar_snoc->pipe_info[pipe_num];
934 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
936 	bitmap_clear(ar_snoc->pending_ce_irqs, 0, CE_COUNT_MAX);
943 	clear_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags);
1018 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1023 	ret = regulator_bulk_enable(ar_snoc->num_vregs, ar_snoc->vregs);
1027 	ret = clk_bulk_prepare_enable(ar_snoc->num_clks, ar_snoc->clks);
1034 	regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs);
1040 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1044 	clk_bulk_disable_unprepare(ar_snoc->num_clks, ar_snoc->clks);
1046 	return regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs);
1051 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1060 	    !test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
1131 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1137 	ret = enable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line);
1150 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1156 	ret = disable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line);
1196 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1200 		if (ar_snoc->ce_irqs[i].irq_line == irq)
1211 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1214 	if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_snoc->pipe_info)) {
1221 	set_bit(ce_id, ar_snoc->pending_ce_irqs);
1231 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1241 		if (test_and_clear_bit(ce_id, ar_snoc->pending_ce_irqs)) {
1261 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1265 		ret = request_irq(ar_snoc->ce_irqs[id].irq_line,
1280 		free_irq(ar_snoc->ce_irqs[id].irq_line, ar);
1287 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1291 		free_irq(ar_snoc->ce_irqs[id].irq_line, ar);
1296 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1301 	pdev = ar_snoc->dev;
1308 	ar_snoc->mem_pa = res->start;
1309 	ar_snoc->mem = devm_ioremap(&pdev->dev, ar_snoc->mem_pa,
1311 	if (!ar_snoc->mem) {
1313 			   &ar_snoc->mem_pa);
1318 		ret = platform_get_irq(ar_snoc->dev, i);
1321 		ar_snoc->ce_irqs[i].irq_line = ret;
1325 				       &ar_snoc->xo_cal_data);
1328 		ar_snoc->xo_cal_supported = true;
1330 			   ar_snoc->xo_cal_data);
1338 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1339 	struct device *dev = &ar_snoc->dev->dev;
1345 		set_bit(ATH10K_SNOC_FLAG_8BIT_HOST_CAP_QUIRK, &ar_snoc->flags);
1350 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1354 	if (test_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags))
1359 		if (test_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags)) {
1365 		bus_params.chip_id = ar_snoc->target_info.soc_version;
1372 		set_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags);
1375 		set_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags);
1388 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1393 	timer_setup(&ar_snoc->rx_post_retry, ath10k_snoc_rx_replenish_retry, 0);
1396 		pipe = &ar_snoc->pipe_info[i];
1491 	struct ath10k_snoc *ar_snoc = container_of(nb, struct ath10k_snoc, nb);
1492 	struct ath10k *ar = ar_snoc->ar;
1498 		clear_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1509 			set_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1511 			clear_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1528 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1532 	ar_snoc->nb.notifier_call = ath10k_snoc_modem_notify;
1534 	notifier = qcom_register_ssr_notifier("mpss", &ar_snoc->nb);
1541 	ar_snoc->notifier = notifier;
1549 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1551 	ret = qcom_unregister_ssr_notifier(ar_snoc->notifier, &ar_snoc->nb);
1602 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1603 	struct device *host_dev = &ar_snoc->dev->dev;
1612 		ar_snoc->use_tz = true;
1636 	ar_snoc->fw.dev = &pdev->dev;
1645 	ret = iommu_attach_device(iommu_dom, ar_snoc->fw.dev);
1651 	ar_snoc->fw.iommu_domain = iommu_dom;
1652 	ar_snoc->fw.fw_start_addr = ar->msa.paddr;
1654 	ret = iommu_map(iommu_dom, ar_snoc->fw.fw_start_addr,
1667 	iommu_detach_device(iommu_dom, ar_snoc->fw.dev);
1681 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1682 	const size_t mapped_size = ar_snoc->fw.mapped_mem_size;
1686 	if (ar_snoc->use_tz)
1689 	iommu = ar_snoc->fw.iommu_domain;
1691 	unmapped_size = iommu_unmap(iommu, ar_snoc->fw.fw_start_addr,
1697 	iommu_detach_device(iommu, ar_snoc->fw.dev);
1700 	platform_device_unregister(to_platform_device(ar_snoc->fw.dev));
1716 	struct ath10k_snoc *ar_snoc;
1736 	ar = ath10k_core_create(sizeof(*ar_snoc), dev, ATH10K_BUS_SNOC,
1743 	ar_snoc = ath10k_snoc_priv(ar);
1744 	ar_snoc->dev = pdev;
1746 	ar_snoc->ar = ar;
1747 	ar_snoc->ce.bus_ops = &ath10k_snoc_bus_ops;
1748 	ar->ce_priv = &ar_snoc->ce;
1770 	ar_snoc->num_vregs = ARRAY_SIZE(ath10k_regulators);
1771 	ar_snoc->vregs = devm_kcalloc(&pdev->dev, ar_snoc->num_vregs,
1772 				      sizeof(*ar_snoc->vregs), GFP_KERNEL);
1773 	if (!ar_snoc->vregs) {
1777 	for (i = 0; i < ar_snoc->num_vregs; i++)
1778 		ar_snoc->vregs[i].supply = ath10k_regulators[i];
1780 	ret = devm_regulator_bulk_get(&pdev->dev, ar_snoc->num_vregs,
1781 				      ar_snoc->vregs);
1785 	ar_snoc->num_clks = ARRAY_SIZE(ath10k_clocks);
1786 	ar_snoc->clks = devm_kcalloc(&pdev->dev, ar_snoc->num_clks,
1787 				     sizeof(*ar_snoc->clks), GFP_KERNEL);
1788 	if (!ar_snoc->clks) {
1793 	for (i = 0; i < ar_snoc->num_clks; i++)
1794 		ar_snoc->clks[i].id = ath10k_clocks[i];
1796 	ret = devm_clk_bulk_get_optional(&pdev->dev, ar_snoc->num_clks,
1797 					 ar_snoc->clks);
1847 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1851 	set_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags);
1867 	struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1873 	if (test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))