ath/ath10k/ahb.c

125 	int ret;
131 		ret = -EIO;
135 	ret = clk_prepare_enable(ar_ahb->cmd_clk);
136 	if (ret) {
137 		ath10k_err(ar, "failed to enable cmd clk: %d\n", ret);
141 	ret = clk_prepare_enable(ar_ahb->ref_clk);
142 	if (ret) {
143 		ath10k_err(ar, "failed to enable ref clk: %d\n", ret);
147 	ret = clk_prepare_enable(ar_ahb->rtc_clk);
148 	if (ret) {
149 		ath10k_err(ar, "failed to enable rtc clk: %d\n", ret);
162 	return ret;
240 	int ret;
250 	ret = reset_control_deassert(ar_ahb->radio_cold_rst);
251 	if (ret) {
252 		ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret);
253 		return ret;
256 	ret = reset_control_deassert(ar_ahb->radio_warm_rst);
257 	if (ret) {
258 		ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret);
259 		return ret;
262 	ret = reset_control_deassert(ar_ahb->radio_srif_rst);
263 	if (ret) {
264 		ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret);
265 		return ret;
268 	ret = reset_control_deassert(ar_ahb->cpu_init_rst);
269 	if (ret) {
270 		ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret);
271 		return ret;
311 	int ret;
347 	ret = reset_control_assert(ar_ahb->core_cold_rst);
348 	if (ret)
349 		ath10k_err(ar, "failed to assert core cold rst: %d\n", ret);
352 	ret = reset_control_assert(ar_ahb->radio_cold_rst);
353 	if (ret)
354 		ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret);
357 	ret = reset_control_assert(ar_ahb->radio_warm_rst);
358 	if (ret)
359 		ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret);
362 	ret = reset_control_assert(ar_ahb->radio_srif_rst);
363 	if (ret)
364 		ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret);
367 	ret = reset_control_assert(ar_ahb->cpu_init_rst);
368 	if (ret)
369 		ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret);
383 	ret = reset_control_deassert(ar_ahb->core_cold_rst);
384 	if (ret)
385 		ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret);
408 	int ret;
410 	ret = request_irq(ar_ahb->irq,
413 	if (ret) {
415 			    ar_ahb->irq, ret);
416 		return ret;
441 	int ret;
448 		ret = PTR_ERR(ar_ahb->mem);
458 		ret = -ENOMEM;
466 		ret = -ENOMEM;
470 	ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
471 	if (ret) {
472 		ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret);
476 	ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
477 	if (ret) {
479 			   ret);
483 	ret = ath10k_ahb_clock_init(ar);
484 	if (ret)
487 	ret = ath10k_ahb_rst_ctrl_init(ar);
488 	if (ret)
494 		ret = ar_ahb->irq;
521 	return ret;
551 	int ret;
553 	ret = ath10k_ahb_clock_enable(ar);
554 	if (ret) {
556 		return ret;
569 	ret = ath10k_ahb_release_reset(ar);
570 	if (ret)
577 	ret = ath10k_pci_wait_for_target_init(ar);
578 	if (ret)
589 	return ret;
594 	int ret;
599 	ret = ath10k_ahb_prepare_device(ar);
600 	if (ret)
601 		return ret;
648 	int ret;
652 	ret = ath10k_ahb_chip_reset(ar);
653 	if (ret) {
654 		ath10k_err(ar, "failed to reset chip: %d\n", ret);
658 	ret = ath10k_pci_init_pipes(ar);
659 	if (ret) {
660 		ath10k_err(ar, "failed to initialize CE: %d\n", ret);
664 	ret = ath10k_pci_init_config(ar);
665 	if (ret) {
666 		ath10k_err(ar, "failed to setup init config: %d\n", ret);
670 	ret = ath10k_ahb_wake_target_cpu(ar);
671 	if (ret) {
672 		ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
681 	return ret;
733 	int ret;
758 	ret = ath10k_ahb_resource_init(ar);
759 	if (ret)
770 	ret = ath10k_pci_setup_resource(ar);
771 	if (ret) {
772 		ath10k_err(ar, "failed to setup resource: %d\n", ret);
778 	ret = ath10k_ahb_request_irq_legacy(ar);
779 	if (ret)
782 	ret = ath10k_ahb_prepare_device(ar);
783 	if (ret)
792 		ret = -ENODEV;
796 	ret = ath10k_core_register(ar, &bus_params);
797 	if (ret) {
798 		ath10k_err(ar, "failed to register driver core: %d\n", ret);
820 	return ret;
850 	int ret;
852 	ret = platform_driver_register(&ath10k_ahb_driver);
853 	if (ret)
855 		       ret);
856 	return ret;