ath/ath10k/ahb.c

28 static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar)
30 	return &ath10k_pci_priv(ar)->ahb[0];
33 static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value)
35 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
40 static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset)
42 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
47 static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset)
49 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
54 static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value)
56 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
61 static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset)
63 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
68 static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr)
70 	return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
73 static int ath10k_ahb_get_num_banks(struct ath10k *ar)
75 	if (ar->hw_rev == ATH10K_HW_QCA4019)
78 	ath10k_warn(ar, "unknown number of banks, assuming 1\n");
82 static int ath10k_ahb_clock_init(struct ath10k *ar)
84 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
91 		ath10k_err(ar, "failed to get cmd clk: %ld\n",
98 		ath10k_err(ar, "failed to get ref clk: %ld\n",
105 		ath10k_err(ar, "failed to get rtc clk: %ld\n",
113 static void ath10k_ahb_clock_deinit(struct ath10k *ar)
115 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
122 static int ath10k_ahb_clock_enable(struct ath10k *ar)
124 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
130 		ath10k_err(ar, "clock(s) is/are not initialized\n");
137 		ath10k_err(ar, "failed to enable cmd clk: %d\n", ret);
143 		ath10k_err(ar, "failed to enable ref clk: %d\n", ret);
149 		ath10k_err(ar, "failed to enable rtc clk: %d\n", ret);
165 static void ath10k_ahb_clock_disable(struct ath10k *ar)
167 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
176 static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar)
178 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
186 		ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n",
194 		ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n",
202 		ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n",
210 		ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n",
218 		ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n",
226 static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar)
228 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
237 static int ath10k_ahb_release_reset(struct ath10k *ar)
239 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
246 		ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");
252 		ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret);
258 		ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret);
264 		ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret);
270 		ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret);
277 static void ath10k_ahb_halt_axi_bus(struct ath10k *ar, u32 haltreq_reg,
284 	val = ath10k_ahb_tcsr_read32(ar, haltreq_reg);
286 	ath10k_ahb_tcsr_write32(ar, haltreq_reg, val);
291 		val = ath10k_ahb_tcsr_read32(ar, haltack_reg);
299 		ath10k_err(ar, "failed to halt axi bus: %d\n", val);
303 	ath10k_dbg(ar, ATH10K_DBG_AHB, "axi bus halted\n");
306 static void ath10k_ahb_halt_chip(struct ath10k *ar)
308 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
318 		ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");
322 	core_id = ath10k_ahb_read32(ar, ATH10K_AHB_WLAN_CORE_ID_REG);
336 		ath10k_err(ar, "invalid core id %d found, skipping reset sequence\n",
341 	ath10k_ahb_halt_axi_bus(ar, haltreq_reg, haltack_reg);
343 	val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg);
345 	ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val);
349 		ath10k_err(ar, "failed to assert core cold rst: %d\n", ret);
354 		ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret);
359 		ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret);
364 		ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret);
369 		ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret);
375 	val = ath10k_ahb_tcsr_read32(ar, haltreq_reg);
377 	ath10k_ahb_tcsr_write32(ar, haltreq_reg, val);
379 	val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg);
381 	ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val);
385 		ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret);
387 	ath10k_dbg(ar, ATH10K_DBG_AHB, "core %d reset done\n", core_id);
392 	struct ath10k *ar = arg;
394 	if (!ath10k_pci_irq_pending(ar))
397 	ath10k_pci_disable_and_clear_legacy_irq(ar);
398 	ath10k_pci_irq_msi_fw_mask(ar);
399 	napi_schedule(&ar->napi);
404 static int ath10k_ahb_request_irq_legacy(struct ath10k *ar)
406 	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
407 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
412 			  IRQF_SHARED, "ath10k_ahb", ar);
414 		ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
423 static void ath10k_ahb_release_irq_legacy(struct ath10k *ar)
425 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
427 	free_irq(ar_ahb->irq, ar);
430 static void ath10k_ahb_irq_disable(struct ath10k *ar)
432 	ath10k_ce_disable_interrupts(ar);
433 	ath10k_pci_disable_and_clear_legacy_irq(ar);
436 static int ath10k_ahb_resource_init(struct ath10k *ar)
438 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
447 		ath10k_err(ar, "mem ioremap error\n");
457 		ath10k_err(ar, "gcc mem ioremap error\n");
465 		ath10k_err(ar, "tcsr mem ioremap error\n");
472 		ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret);
478 		ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n",
483 	ret = ath10k_ahb_clock_init(ar);
487 	ret = ath10k_ahb_rst_ctrl_init(ar);
493 		ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq);
498 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq);
500 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "mem: 0x%pK mem_len: %lu gcc mem: 0x%pK tcsr_mem: 0x%pK\n",
506 	ath10k_ahb_clock_deinit(ar);
524 static void ath10k_ahb_resource_deinit(struct ath10k *ar)
526 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
544 	ath10k_ahb_clock_deinit(ar);
545 	ath10k_ahb_rst_ctrl_deinit(ar);
548 static int ath10k_ahb_prepare_device(struct ath10k *ar)
553 	ret = ath10k_ahb_clock_enable(ar);
555 		ath10k_err(ar, "failed to enable clocks\n");
566 	val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV);
567 	ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val);
569 	ret = ath10k_ahb_release_reset(ar);
573 	ath10k_ahb_irq_disable(ar);
575 	ath10k_ahb_write32(ar, FW_INDICATOR_ADDRESS, FW_IND_HOST_READY);
577 	ret = ath10k_pci_wait_for_target_init(ar);
584 	ath10k_ahb_halt_chip(ar);
587 	ath10k_ahb_clock_disable(ar);
592 static int ath10k_ahb_chip_reset(struct ath10k *ar)
596 	ath10k_ahb_halt_chip(ar);
597 	ath10k_ahb_clock_disable(ar);
599 	ret = ath10k_ahb_prepare_device(ar);
606 static int ath10k_ahb_wake_target_cpu(struct ath10k *ar)
611 	val = ath10k_ahb_read32(ar, addr);
613 	ath10k_ahb_write32(ar, addr, val);
618 static int ath10k_ahb_hif_start(struct ath10k *ar)
620 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif start\n");
622 	ath10k_core_napi_enable(ar);
623 	ath10k_ce_enable_interrupts(ar);
624 	ath10k_pci_enable_legacy_irq(ar);
626 	ath10k_pci_rx_post(ar);
631 static void ath10k_ahb_hif_stop(struct ath10k *ar)
633 	struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
635 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif stop\n");
637 	ath10k_ahb_irq_disable(ar);
640 	ath10k_core_napi_sync_disable(ar);
642 	ath10k_pci_flush(ar);
645 static int ath10k_ahb_hif_power_up(struct ath10k *ar,
650 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif power up\n");
652 	ret = ath10k_ahb_chip_reset(ar);
654 		ath10k_err(ar, "failed to reset chip: %d\n", ret);
658 	ret = ath10k_pci_init_pipes(ar);
660 		ath10k_err(ar, "failed to initialize CE: %d\n", ret);
664 	ret = ath10k_pci_init_config(ar);
666 		ath10k_err(ar, "failed to setup init config: %d\n", ret);
670 	ret = ath10k_ahb_wake_target_cpu(ar);
672 		ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
679 	ath10k_pci_ce_deinit(ar);
684 static u32 ath10k_ahb_qca4019_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
688 	val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
728 	struct ath10k *ar;
743 	ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB,
745 	if (!ar) {
750 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "ahb probe\n");
752 	ar_pci = ath10k_pci_priv(ar);
753 	ar_ahb = ath10k_ahb_priv(ar);
756 	platform_set_drvdata(pdev, ar);
758 	ret = ath10k_ahb_resource_init(ar);
762 	ar->dev_id = 0;
765 	ar_pci->ar = ar;
768 	ar->ce_priv = &ar_pci->ce;
770 	ret = ath10k_pci_setup_resource(ar);
772 		ath10k_err(ar, "failed to setup resource: %d\n", ret);
776 	ath10k_pci_init_napi(ar);
778 	ret = ath10k_ahb_request_irq_legacy(ar);
782 	ret = ath10k_ahb_prepare_device(ar);
786 	ath10k_pci_ce_deinit(ar);
789 	bus_params.chip_id = ath10k_ahb_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
791 		ath10k_err(ar, "failed to get chip id\n");
796 	ret = ath10k_core_register(ar, &bus_params);
798 		ath10k_err(ar, "failed to register driver core: %d\n", ret);
805 	ath10k_ahb_halt_chip(ar);
806 	ath10k_ahb_clock_disable(ar);
809 	ath10k_ahb_release_irq_legacy(ar);
812 	ath10k_pci_release_resource(ar);
815 	ath10k_ahb_resource_deinit(ar);
818 	ath10k_core_destroy(ar);
825 	struct ath10k *ar = platform_get_drvdata(pdev);
827 	ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n");
829 	ath10k_core_unregister(ar);
830 	ath10k_ahb_irq_disable(ar);
831 	ath10k_ahb_release_irq_legacy(ar);
832 	ath10k_pci_release_resource(ar);
833 	ath10k_ahb_halt_chip(ar);
834 	ath10k_ahb_clock_disable(ar);
835 	ath10k_ahb_resource_deinit(ar);
836 	ath10k_core_destroy(ar);