Lines Matching refs:a0
291 movel ch_status_addr(%d0), %a0 // A0 = port status address
292 tstl STATUS_OPEN(%a0)
294 movel #1, STATUS_OPEN(%a0) // confirm the port is open
303 cmpl #CLOCK_TXFROMRX, STATUS_CLOCKING(%a0)
321 cmpl #PARITY_NONE, STATUS_PARITY(%a0)
360 cmpl #PARITY_CRC16_PR1_CCITT, STATUS_PARITY(%a0)
370 cmpl #PARITY_CRC32_PR1_CCITT, STATUS_PARITY(%a0)
380 cmpl #PARITY_CRC16_PR0_CCITT, STATUS_PARITY(%a0)
390 cmpl #PARITY_CRC32_PR0_CCITT, STATUS_PARITY(%a0)
408 cmpl #ENCODING_NRZI, STATUS_ENCODING(%a0)
433 movel scc_reg_addr(%d0), %a0 // A0 = SCC_REGS address
434 clrw SCC_SCCM(%a0) // no SCC interrupts
435 andl #0xFFFFFFCF, SCC_GSMR_L(%a0) // Disable ENT and ENR
460 movel 4(%d2), %a0 // PCI address
467 memcpy_from_pci %a0, %a1, %d2
518 movel 4(%d1), %a0 // A0 = source address
522 memcpy_to_pci %a0, %a1, %d3
688 movel %a0, -(%sp)
692 movel #CSRA, %a0 // A0 = CSR address
695 movew (%a0), %d1 // D1 = CSR input bits
735 movew %d1, (%a0) // Write CSR output bits
741 movew (%a0), %d1 // D1 = CSR input bits
746 movew (%a0), %d1 // D1 = CSR input bits
757 addl #2, %a0 // next CSR register
763 movel (%sp)+, %a0
786 movel %d0, %a0
787 addl #128 * 1024 - 4, %a0
788 cmpl (%a0), %d1
797 cmpl (%a0), %d1
801 movel %d0, %a0 // A0 = fill ptr
806 movel %a0, -(%a0)
813 cmpl (%a0)+, %a0
822 subl #4, %a0
824 movel %a0, PLX_MAILBOX_5