net/wan/slic_ds26522.c

38 static void slic_write(struct spi_device *spi, u16 addr,
83 	slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_E1);
86 	slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_E1);
89 	slic_write(spi, DS26522_RMMR_ADDR,
93 	slic_write(spi, DS26522_TMMR_ADDR,
97 	slic_write(spi, DS26522_RCR1_ADDR,
101 	slic_write(spi, DS26522_RIOCR_ADDR,
105 	slic_write(spi, DS26522_TCR1_ADDR, DS26522_TCR1_TB8ZS);
108 	slic_write(spi, DS26522_TIOCR_ADDR,
112 	slic_write(spi, DS26522_E1TAF_ADDR, DS26522_E1TAF_DEFAULT);
115 	slic_write(spi, DS26522_E1TNAF_ADDR, DS26522_E1TNAF_DEFAULT);
118 	slic_write(spi, DS26522_RMMR_ADDR, slic_read(spi, DS26522_RMMR_ADDR) |
122 	slic_write(spi, DS26522_TMMR_ADDR, slic_read(spi, DS26522_TMMR_ADDR) |
126 	slic_write(spi, DS26522_LTRCR_ADDR, DS26522_LTRCR_E1);
129 	slic_write(spi, DS26522_LTITSR_ADDR,
133 	slic_write(spi, DS26522_LRISMR_ADDR,
137 	slic_write(spi, DS26522_LMCR_ADDR, DS26522_LMCR_TE);
145 	slic_write(spi, DS26522_GTCCR_ADDR, DS26522_GTCCR_BPREFSEL_REFCLKIN |
148 	slic_write(spi, DS26522_GTCR2_ADDR, DS26522_GTCR2_TSSYNCOUT);
149 	slic_write(spi, DS26522_GFCR_ADDR, DS26522_GFCR_BPCLK_2048KHZ);
152 	slic_write(spi, DS26522_GTCR1_ADDR, DS26522_GTCR1);
155 	slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_RESET);
158 	slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_RESET);
162 	slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_NORMAL);
163 	slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_NORMAL);
166 	slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_SFTRST);
169 	slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_SFTRST);
176 		slic_write(spi, addr, 0);
180 		slic_write(spi, addr, 0);
184 		slic_write(spi, addr, 0);
188 		slic_write(spi, addr, 0);
193 	slic_write(spi, DS26522_GTCR1_ADDR, 0x00);