net/vmxnet3/vmxnet3_drv.c

404 	union Vmxnet3_GenericDesc *gdesc;
411 	gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
412 	while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
413 		/* Prevent any &gdesc->tcd field from being (speculatively)
414 		 * read before (&gdesc->tcd)->gen is read.
419 					       &gdesc->tcd), tq, adapter->pdev,
423 		gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
741 	union Vmxnet3_GenericDesc *gdesc;
750 	gdesc = ctx->sop_txd; /* both loops below can be skipped */
798 		gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
799 		BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
801 		gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
802 		gdesc->dword[2] = cpu_to_le32(dw2);
803 		gdesc->dword[3] = 0;
807 			tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
808 			le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
840 			gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
841 			BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
843 			gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
844 			gdesc->dword[2] = cpu_to_le32(dw2);
845 			gdesc->dword[3] = 0;
849 				tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
850 				le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
859 	ctx->eop_txd = gdesc;
1090 	union Vmxnet3_GenericDesc *gdesc;
1201 	gdesc = &tempTxDesc;
1202 	gdesc->dword[2] = ctx.sop_txd->dword[2];
1203 	gdesc->dword[3] = ctx.sop_txd->dword[3];
1205 	gdesc = ctx.sop_txd;
1210 			gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1212 				gdesc->txd.om = VMXNET3_OM_TSO;
1213 				gdesc->txd.ext1 = 1;
1215 				gdesc->txd.om = VMXNET3_OM_ENCAP;
1217 			gdesc->txd.msscof = ctx.mss;
1220 				gdesc->txd.oco = 1;
1222 			gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1223 			gdesc->txd.om = VMXNET3_OM_TSO;
1224 			gdesc->txd.msscof = ctx.mss;
1226 		num_pkts = (skb->len - gdesc->txd.hlen + ctx.mss - 1) / ctx.mss;
1231 				gdesc->txd.hlen = ctx.l4_offset +
1234 					gdesc->txd.om = VMXNET3_OM_CSUM;
1235 					gdesc->txd.msscof = ctx.l4_offset +
1237 					gdesc->txd.ext1 = 1;
1239 					gdesc->txd.om = VMXNET3_OM_ENCAP;
1240 					gdesc->txd.msscof = 0;		/* Reserved */
1243 				gdesc->txd.hlen = ctx.l4_offset;
1244 				gdesc->txd.om = VMXNET3_OM_CSUM;
1245 				gdesc->txd.msscof = ctx.l4_offset +
1249 			gdesc->txd.om = 0;
1250 			gdesc->txd.msscof = 0;
1258 		gdesc->txd.ti = 1;
1259 		gdesc->txd.tci = skb_vlan_tag_get(skb);
1262 	/* Ensure that the write to (&gdesc->txd)->gen will be observed after
1263 	 * all other writes to &gdesc->txd.
1268 	gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1274 	vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1276 	gdesc = ctx.sop_txd;
1281 		tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1282 		le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
1376 		union Vmxnet3_GenericDesc *gdesc)
1378 	if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
1379 		if (gdesc->rcd.v4 &&
1380 		    (le32_to_cpu(gdesc->dword[3]) &
1383 			if ((le32_to_cpu(gdesc->dword[0]) &
1387 			WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1388 				     !(le32_to_cpu(gdesc->dword[0]) &
1390 			WARN_ON_ONCE(gdesc->rcd.frg &&
1391 				     !(le32_to_cpu(gdesc->dword[0]) &
1393 		} else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) &
1396 			if ((le32_to_cpu(gdesc->dword[0]) &
1400 			WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1401 				     !(le32_to_cpu(gdesc->dword[0]) &
1403 			WARN_ON_ONCE(gdesc->rcd.frg &&
1404 				     !(le32_to_cpu(gdesc->dword[0]) &
1407 			if (gdesc->rcd.csum) {
1408 				skb->csum = htons(gdesc->rcd.csum);
1449 		    union Vmxnet3_GenericDesc *gdesc)
1460 	BUG_ON(gdesc->rcd.tcp == 0);
1473 	if (gdesc->rcd.v4) {
1480 	} else if (gdesc->rcd.v6) {
1694 				union Vmxnet3_GenericDesc *gdesc;
1697 				gdesc = (union Vmxnet3_GenericDesc *)rcd;
1704 				encap_lro = (le32_to_cpu(gdesc->dword[0]) &