Lines Matching refs:ret
80 int ret;
90 ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
93 if (unlikely(ret < 4)) {
94 ret = ret < 0 ? ret : -ENODATA;
97 index, ret);
98 return ret;
104 return ret;
111 int ret;
124 ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
127 if (unlikely(ret < 0))
129 index, ret);
131 return ret;
165 int ret;
168 ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
169 if (ret < 0) {
171 return ret;
186 int ret;
191 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
192 if (ret < 0) {
203 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
204 if (ret < 0) {
209 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
210 if (ret < 0) {
215 ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
216 if (ret < 0) {
221 ret = (u16)(val & 0xFFFF);
225 return ret;
233 int ret;
238 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
239 if (ret < 0) {
245 ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
246 if (ret < 0) {
257 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
258 if (ret < 0) {
263 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
264 if (ret < 0) {
300 int ret;
303 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
304 if (ret < 0) {
306 return ret;
326 int ret;
329 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
330 if (ret < 0) {
332 return ret;
349 int i, ret;
354 ret = smsc75xx_eeprom_confirm_not_busy(dev);
355 if (ret)
356 return ret;
360 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
361 if (ret < 0) {
363 return ret;
366 ret = smsc75xx_wait_eeprom(dev);
367 if (ret < 0)
368 return ret;
370 ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
371 if (ret < 0) {
373 return ret;
387 int i, ret;
392 ret = smsc75xx_eeprom_confirm_not_busy(dev);
393 if (ret)
394 return ret;
398 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
399 if (ret < 0) {
401 return ret;
404 ret = smsc75xx_wait_eeprom(dev);
405 if (ret < 0)
406 return ret;
412 ret = smsc75xx_write_reg(dev, E2P_DATA, val);
413 if (ret < 0) {
415 return ret;
420 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
421 if (ret < 0) {
423 return ret;
426 ret = smsc75xx_wait_eeprom(dev);
427 if (ret < 0)
428 return ret;
438 int i, ret;
442 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
443 if (ret < 0) {
445 return ret;
464 int i, ret;
468 ret = smsc75xx_dataport_wait_not_busy(dev);
469 if (ret < 0) {
474 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
475 if (ret < 0) {
482 ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
483 if (ret < 0) {
489 ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
490 if (ret < 0) {
495 ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
496 if (ret < 0) {
501 ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
502 if (ret < 0) {
507 ret = smsc75xx_dataport_wait_not_busy(dev);
508 if (ret < 0) {
516 return ret;
530 int ret;
538 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
539 if (ret < 0)
592 int ret;
613 ret = smsc75xx_write_reg(dev, FLOW, flow);
614 if (ret < 0) {
616 return ret;
619 ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
620 if (ret < 0) {
622 return ret;
633 int ret;
639 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
640 if (ret < 0) {
642 return ret;
721 int ret;
728 ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
729 if (ret < 0)
730 netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
732 return ret;
795 int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
796 if (ret < 0) {
797 netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
798 return ret;
801 ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
802 if (ret < 0) {
803 netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
804 return ret;
808 ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
809 if (ret < 0) {
810 netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
811 return ret;
814 ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
815 if (ret < 0)
816 netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
818 return ret;
823 int bmcr, ret, timeout = 0;
862 ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
863 if (ret < 0) {
865 return ret;
880 int ret = 0;
884 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
885 if (ret < 0) {
886 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
887 return ret;
894 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
895 if (ret < 0) {
896 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
897 return ret;
905 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
906 if (ret < 0) {
907 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
908 return ret;
913 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
914 if (ret < 0) {
915 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
916 return ret;
926 int ret;
928 ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
929 if (ret < 0) {
931 return ret;
944 int ret;
956 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
957 if (ret < 0) {
959 return ret;
970 int ret;
972 ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
974 if (ret < 0) {
975 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
976 return ret;
993 int ret = 0, timeout = 0;
1012 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1013 if (ret < 0) {
1014 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1015 return ret;
1020 ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
1021 if (ret < 0) {
1022 netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
1023 return ret;
1029 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1030 if (ret < 0) {
1032 ret);
1033 return ret;
1050 int ret = 0, timeout;
1054 ret = smsc75xx_wait_ready(dev, 0);
1055 if (ret < 0) {
1057 return ret;
1060 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1061 if (ret < 0) {
1062 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1063 return ret;
1068 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1069 if (ret < 0) {
1070 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1071 return ret;
1077 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1078 if (ret < 0) {
1079 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1080 return ret;
1092 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1093 if (ret < 0) {
1094 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1095 return ret;
1100 ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
1101 if (ret < 0) {
1102 netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
1103 return ret;
1109 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1110 if (ret < 0) {
1111 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1112 return ret;
1124 ret = smsc75xx_set_mac_address(dev);
1125 if (ret < 0) {
1127 return ret;
1133 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1134 if (ret < 0) {
1135 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1136 return ret;
1144 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1145 if (ret < 0) {
1146 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1147 return ret;
1150 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1151 if (ret < 0) {
1152 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1153 return ret;
1173 ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
1174 if (ret < 0) {
1175 netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
1176 return ret;
1179 ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
1180 if (ret < 0) {
1181 netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
1182 return ret;
1188 ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
1189 if (ret < 0) {
1190 netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
1191 return ret;
1194 ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
1195 if (ret < 0) {
1196 netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
1197 return ret;
1204 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1205 if (ret < 0) {
1206 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1207 return ret;
1214 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1215 if (ret < 0) {
1216 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1217 return ret;
1220 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1221 if (ret < 0) {
1222 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1223 return ret;
1231 ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
1232 if (ret < 0) {
1233 netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
1234 return ret;
1240 ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
1241 if (ret < 0) {
1242 netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
1243 return ret;
1248 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
1249 if (ret < 0) {
1250 netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
1251 return ret;
1254 ret = smsc75xx_read_reg(dev, ID_REV, &buf);
1255 if (ret < 0) {
1256 netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
1257 return ret;
1262 ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
1263 if (ret < 0) {
1264 netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
1265 return ret;
1270 ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
1271 if (ret < 0) {
1272 netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
1273 return ret;
1279 ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
1280 if (ret < 0) {
1281 netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
1282 return ret;
1286 ret = smsc75xx_write_reg(dev, FLOW, 0);
1287 if (ret < 0) {
1288 netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
1289 return ret;
1292 ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
1293 if (ret < 0) {
1294 netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
1295 return ret;
1299 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
1300 if (ret < 0) {
1301 netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
1302 return ret;
1307 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
1308 if (ret < 0) {
1309 netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
1310 return ret;
1313 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
1314 if (ret < 0) {
1315 netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
1316 return ret;
1327 ret = smsc75xx_phy_initialize(dev);
1328 if (ret < 0) {
1329 netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
1330 return ret;
1333 ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
1334 if (ret < 0) {
1335 netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
1336 return ret;
1342 ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
1343 if (ret < 0) {
1344 netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
1345 return ret;
1349 ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
1350 if (ret < 0) {
1351 netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
1352 return ret;
1356 ret = smsc75xx_write_reg(dev, MAC_CR, buf);
1357 if (ret < 0) {
1358 netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
1359 return ret;
1362 ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
1363 if (ret < 0) {
1364 netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
1365 return ret;
1370 ret = smsc75xx_write_reg(dev, MAC_TX, buf);
1371 if (ret < 0) {
1372 netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
1373 return ret;
1378 ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
1379 if (ret < 0) {
1380 netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
1381 return ret;
1386 ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
1387 if (ret < 0) {
1388 netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
1389 return ret;
1394 ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
1395 if (ret < 0) {
1397 return ret;
1400 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
1401 if (ret < 0) {
1402 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
1403 return ret;
1408 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
1409 if (ret < 0) {
1410 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
1411 return ret;
1416 ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
1417 if (ret < 0) {
1418 netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
1419 return ret;
1424 ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
1425 if (ret < 0) {
1426 netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
1427 return ret;
1453 int ret;
1457 ret = usbnet_get_endpoints(dev, intf);
1458 if (ret < 0) {
1459 netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
1460 return ret;
1486 ret = smsc75xx_wait_ready(dev, 0);
1487 if (ret < 0) {
1495 ret = smsc75xx_reset(dev);
1496 if (ret < 0) {
1497 netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
1514 return ret;
1538 int ret;
1540 ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
1541 if (ret < 0) {
1543 return ret;
1546 ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
1547 if (ret < 0) {
1549 return ret;
1552 ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
1553 if (ret < 0) {
1555 return ret;
1558 ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
1559 if (ret < 0) {
1561 return ret;
1564 ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
1565 if (ret < 0) {
1567 return ret;
1577 int ret;
1579 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1580 if (ret < 0) {
1582 return ret;
1588 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1589 if (ret < 0) {
1591 return ret;
1603 int ret;
1605 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1606 if (ret < 0) {
1608 return ret;
1614 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1615 if (ret < 0) {
1617 return ret;
1624 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1625 if (ret < 0) {
1627 return ret;
1639 int ret;
1641 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1642 if (ret < 0) {
1644 return ret;
1650 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1651 if (ret < 0) {
1653 return ret;
1665 int ret;
1667 ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
1668 if (ret < 0) {
1670 return ret;
1678 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1679 if (ret < 0) {
1681 return ret;
1687 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1688 if (ret < 0) {
1690 return ret;
1697 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1698 if (ret < 0) {
1700 return ret;
1711 int ret;
1716 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
1717 if (ret < 0) {
1719 return ret;
1723 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
1724 if (ret < 0) {
1726 return ret;
1729 ret |= mask;
1731 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
1739 int ret;
1742 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
1743 if (ret < 0) {
1745 return ret;
1748 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
1749 if (ret < 0) {
1751 return ret;
1754 return !!(ret & BMSR_LSTATUS);
1759 int ret;
1772 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1774 if (ret < 0) {
1776 return ret;
1784 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1786 if (ret < 0) {
1788 return ret;
1800 int ret;
1802 ret = usbnet_suspend(intf, message);
1803 if (ret < 0) {
1805 return ret;
1817 ret = smsc75xx_autosuspend(dev, link_up);
1830 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
1831 if (ret < 0) {
1838 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
1839 if (ret < 0) {
1844 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1845 if (ret < 0) {
1852 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1853 if (ret < 0) {
1858 ret = smsc75xx_enter_suspend2(dev);
1863 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1865 if (ret < 0) {
1878 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
1880 if (ret < 0) {
1885 ret |= MODE_CTRL_STS_EDPWRDOWN;
1888 PHY_MODE_CTRL_STS, ret);
1891 ret = smsc75xx_enter_suspend1(dev);
1901 ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
1902 if (ret < 0) {
1914 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
1915 if (ret < 0) {
1927 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
1928 if (ret < 0) {
1935 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
1936 if (ret < 0) {
1943 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
1944 if (ret < 0) {
1950 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
1951 if (ret < 0) {
1958 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
1959 if (ret < 0) {
1965 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
1966 if (ret < 0) {
1973 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
1974 if (ret < 0) {
1981 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
1982 if (ret < 0) {
1989 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
1990 if (ret < 0) {
1998 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1999 if (ret < 0) {
2008 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
2009 if (ret < 0) {
2017 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
2018 if (ret < 0) {
2026 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
2027 if (ret < 0) {
2035 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
2036 if (ret < 0) {
2043 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
2044 if (ret < 0) {
2052 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
2053 if (ret < 0) {
2060 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
2061 if (ret < 0) {
2068 ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
2069 if (ret < 0) {
2070 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
2076 ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
2077 if (ret < 0) {
2078 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
2084 ret = smsc75xx_enter_suspend0(dev);
2091 if (ret && PMSG_IS_AUTO(message))
2093 return ret;
2101 int ret;
2111 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
2112 if (ret < 0) {
2114 return ret;
2120 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
2121 if (ret < 0) {
2123 return ret;
2127 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
2128 if (ret < 0) {
2130 return ret;
2136 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
2137 if (ret < 0) {
2139 return ret;
2146 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
2147 if (ret < 0) {
2149 return ret;
2154 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
2155 if (ret < 0) {
2157 return ret;
2161 ret = smsc75xx_wait_ready(dev, 1);
2162 if (ret < 0) {
2164 return ret;