net/phy/smsc.c

61 	int rc = phy_read(phydev, MII_LAN83C185_ISF);
63 	return rc < 0 ? rc : 0;
68 	int rc;
71 		rc = smsc_phy_ack_interrupt(phydev);
72 		if (rc)
73 			return rc;
75 		rc = phy_write(phydev, MII_LAN83C185_IM,
78 		rc = phy_write(phydev, MII_LAN83C185_IM, 0);
79 		if (rc)
80 			return rc;
82 		rc = smsc_phy_ack_interrupt(phydev);
85 	return rc < 0 ? rc : 0;
139 	int rc = phy_read(phydev, MII_LAN83C185_SPECIAL_MODES);
140 	if (rc < 0)
141 		return rc;
146 	if ((rc & MII_LAN83C185_MODE_MASK) == MII_LAN83C185_MODE_POWERDOWN) {
148 		rc |= MII_LAN83C185_MODE_ALL;
149 		phy_write(phydev, MII_LAN83C185_SPECIAL_MODES, rc);
158 	int rc;
176 	rc = phy_read(phydev, SPECIAL_CTRL_STS);
177 	if (rc < 0)
178 		return rc;
180 	rc &= ~(SPECIAL_CTRL_STS_OVRRD_AMDIX_ |
183 	rc |= val;
184 	phy_write(phydev, SPECIAL_CTRL_STS, rc);
194 		int rc = phy_set_bits(phydev, PHY_EDPD_CONFIG,
197 		if (rc < 0)
198 			return rc;
227 		int rc;
230 		rc = phy_read(phydev, MII_LAN83C185_CTRL_STATUS);
231 		if (rc < 0)
232 			return rc;
234 		rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS,
235 			       rc & ~MII_LAN83C185_EDPWRDOWN);
236 		if (rc < 0)
237 			return rc;
242 		read_poll_timeout(phy_read, rc,
243 				  rc & MII_LAN83C185_ENERGYON || rc < 0,
246 		if (rc < 0)
247 			return rc;
250 		rc = phy_read(phydev, MII_LAN83C185_CTRL_STATUS);
251 		if (rc < 0)
252 			return rc;
254 		rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS,
255 			       rc | MII_LAN83C185_EDPWRDOWN);
256 		if (rc < 0)
257 			return rc;
267 	int rc;
280 	rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR,
282 	if (rc < 0)
283 		return rc;
286 	rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_MCFGR,
288 	if (rc < 0)
289 		return rc;
298 	int rc;
304 	rc = phy_read_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR);
305 	if (rc < 0)
308 	if (rc & MII_LAN874X_PHY_WOL_PFDAEN)
311 	if (rc & MII_LAN874X_PHY_WOL_BCSTEN)
314 	if (rc & MII_LAN874X_PHY_WOL_MPEN)
317 	if (rc & MII_LAN874X_PHY_WOL_WUEN) {
372 	int rc;
376 	rc = phy_write_mmd(phydev, MDIO_MMD_PCS,
378 	if (rc < 0)
379 		return rc;
382 	rc = phy_write_mmd(phydev, MDIO_MMD_PCS,
384 	if (rc < 0)
385 		return rc;
390 		rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg, *mask);
391 		if (rc < 0)
392 			return rc;
403 	return rc;
414 	int rc;
424 	rc = phy_read_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR);
425 	if (rc < 0)
426 		return rc;
428 	val_wucsr = rc;
455 		rc = lan874x_chk_wol_pattern(pattern, mask, 2, data,
457 		if (rc)
458 			phydev_dbg(phydev, "pattern not valid at %d\n", rc);
464 		rc = lan874x_set_wol_pattern(phydev, val, data, datalen, mask,
466 		if (rc < 0)
467 			return rc;
474 		rc = lan874x_set_wol_pattern(phydev, val, data, 0, NULL, 0);
475 		if (rc < 0)
476 			return rc;
486 			rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg,
488 			if (rc < 0)
489 				return rc;
493 	rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR,
495 	if (rc < 0)
496 		return rc;