phy/qcom/qca808x.c

98 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
103 	ret = genphy_c45_fast_retrain(phydev, true);
107 	phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
109 	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
111 	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
113 	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
115 	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
117 	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
119 	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
121 	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
123 	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
125 	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
127 	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
133 static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
138 		return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
142 	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
148 static bool qca808x_is_prefer_master(struct phy_device *phydev)
150 	return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
151 		(phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
154 static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
156 	return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
159 static bool qca808x_is_1g_only(struct phy_device *phydev)
163 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
170 static void qca808x_fill_possible_interfaces(struct phy_device *phydev)
172 	unsigned long *possible = phydev->possible_interfaces;
176 	if (!qca808x_is_1g_only(phydev))
180 static int qca808x_probe(struct phy_device *phydev)
182 	struct device *dev = &phydev->mdio.dev;
192 	phydev->priv = priv;
197 static int qca808x_config_init(struct phy_device *phydev)
199 	struct qca808x_priv *priv = phydev->priv;
204 		ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN,
212 	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
218 	ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
224 	if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
226 		ret = qca808x_phy_fast_retrain_config(phydev);
230 		ret = genphy_read_master_slave(phydev);
234 		if (!qca808x_is_prefer_master(phydev)) {
238 			ret = qca808x_phy_ms_seed_enable(phydev, true);
244 	qca808x_fill_possible_interfaces(phydev);
247 	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
252 static int qca808x_read_status(struct phy_device *phydev)
257 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
261 	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
264 	ret = genphy_read_status(phydev);
271 	ret = at803x_read_specific_status(phydev, ss_mask);
275 	if (phydev->link) {
276 		if (phydev->speed == SPEED_2500)
277 			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
279 			phydev->interface = PHY_INTERFACE_MODE_SGMII;
290 		if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
291 			if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
292 			    qca808x_is_prefer_master(phydev)) {
293 				qca808x_phy_ms_seed_enable(phydev, false);
295 				qca808x_phy_ms_seed_enable(phydev, true);
303 static int qca808x_soft_reset(struct phy_device *phydev)
307 	ret = genphy_soft_reset(phydev);
311 	if (qca808x_has_fast_retrain_or_slave_seed(phydev))
312 		ret = qca808x_phy_ms_seed_enable(phydev, true);
317 static int qca808x_cable_test_start(struct phy_device *phydev)
328 	ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
332 	ret = at803x_config_mdix(phydev, ETH_TP_MDI);
337 	phydev->duplex = DUPLEX_FULL;
338 	phydev->speed = SPEED_1000;
339 	ret = genphy_c45_pma_setup_forced(phydev);
343 	ret = genphy_setup_forced(phydev);
348 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
349 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
350 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
351 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
352 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
353 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
358 static int qca808x_get_features(struct phy_device *phydev)
362 	ret = genphy_c45_pma_read_abilities(phydev);
370 	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
376 	if (qca808x_is_1g_only(phydev))
377 		linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
382 static int qca808x_config_aneg(struct phy_device *phydev)
387 	ret = at803x_prepare_config_aneg(phydev);
394 	if (phydev->autoneg == AUTONEG_DISABLE)
395 		genphy_c45_pma_setup_forced(phydev);
397 	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
400 	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
405 	return __genphy_config_aneg(phydev, ret);
408 static void qca808x_link_change_notify(struct phy_device *phydev)
413 	mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
416 				   phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
419 static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
451 static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
459 	return qca808x_led_reg_hw_control_enable(phydev, reg);
462 static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
470 	return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
473 static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
484 	ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
488 	ret = qca808x_led_hw_control_enable(phydev, index);
492 	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
497 static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
505 	return qca808x_led_reg_hw_control_status(phydev, reg);
508 static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
518 	if (qca808x_led_hw_control_status(phydev, index))
523 	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
544 static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
553 	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
557 static int qca808x_led_brightness_set(struct phy_device *phydev,
567 		ret = qca808x_led_hw_control_reset(phydev, index);
573 	return qca808x_led_reg_brightness_set(phydev, reg, value);
576 static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
586 	return qca808x_led_reg_blink_set(phydev, reg, delay_on, delay_off);
589 static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
592 	struct qca808x_priv *priv = phydev->priv;
612 		phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
619 	return phy_modify_mmd(phydev, MDIO_MMD_AN,