Lines Matching refs:val

19 	int val;
22 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
23 if (val < 0)
26 phydev->pma_extable = val;
399 int val;
404 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
406 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0;
421 int val, devad;
425 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
426 if (val < 0)
427 return val;
432 if (val & MDIO_AN_CTRL1_RESTART) {
448 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
449 if (val < 0)
450 return val;
451 else if (val & MDIO_STAT1_LSTATUS)
455 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
456 if (val < 0)
457 return val;
459 if (!(val & MDIO_STAT1_LSTATUS))
476 int val;
478 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
479 if (val < 0)
480 return val;
482 if (!(val & MDIO_AN_STAT1_COMPLETE)) {
495 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L);
496 if (val < 0)
497 return val;
499 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val);
500 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0;
501 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0;
503 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M);
504 if (val < 0)
505 return val;
507 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val);
524 int val;
529 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
530 if (val < 0)
531 return val;
533 if (!(val & MDIO_AN_STAT1_COMPLETE)) {
545 val & MDIO_AN_STAT1_LPABLE);
548 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
549 if (val < 0)
550 return val;
552 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val);
553 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0;
554 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0;
557 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
558 if (val < 0)
559 return val;
561 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
574 int val;
579 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL);
580 if (val < 0)
581 return val;
583 if (val & MDIO_PMA_PMD_BT1_CTRL_CFG_MST) {
601 int val;
605 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
606 if (val < 0)
607 return val;
609 switch (val & MDIO_CTRL1_SPEEDSEL) {
636 val = genphy_c45_pma_baset1_read_master_slave(phydev);
637 if (val < 0)
638 return val;
651 int val;
654 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
656 if (val < 0)
657 return val;
659 switch (val) {
685 int val, changed = 0;
688 val = linkmode_to_mii_eee_cap1_t(adv);
693 val &= ~phydev->eee_broken_modes;
698 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
703 val);
704 if (val < 0)
705 return val;
706 if (val > 0)
711 val = linkmode_to_mii_eee_cap2_t(adv);
716 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
719 val);
720 if (val < 0)
721 return val;
722 if (val > 0)
728 val = linkmode_adv_to_mii_10base_t1_t(adv);
732 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
735 val);
736 if (val < 0)
737 return val;
738 if (val > 0)
752 int val;
758 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
759 if (val < 0)
760 return val;
762 mii_eee_cap1_mod_linkmode_t(adv, val);
769 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
770 if (val < 0)
771 return val;
773 mii_eee_cap2_mod_linkmode_adv_t(adv, val);
781 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL);
782 if (val < 0)
783 return val;
785 mii_10base_t1_adv_mod_linkmode_t(adv, val);
799 int val;
805 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
806 if (val < 0)
807 return val;
809 mii_eee_cap1_mod_linkmode_t(lpa, val);
816 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE2);
817 if (val < 0)
818 return val;
820 mii_eee_cap2_mod_linkmode_adv_t(lpa, val);
828 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT);
829 if (val < 0)
830 return val;
832 mii_10base_t1_adv_mod_linkmode_t(lpa, val);
844 int val;
849 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
850 if (val < 0)
851 return val;
858 if (val == 0xffff)
861 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val);
878 int val;
883 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2);
884 if (val < 0)
885 return val;
888 if (val == 0xffff)
891 mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val);
902 int val;
909 val = genphy_c45_read_eee_cap1(phydev);
910 if (val)
911 return val;
916 val = genphy_c45_read_eee_cap2(phydev);
917 if (val)
918 return val;
926 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);
927 if (val < 0)
928 return val;
932 val & MDIO_PMA_10T1L_STAT_EEE);
962 int val;
964 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1);
965 if (val < 0)
966 return val;
970 val & MDIO_PMA_PMD_BT1_B10L_ABLE);
974 val & MDIO_PMA_PMD_BT1_B100_ABLE);
978 val & MDIO_PMA_PMD_BT1_B1000_ABLE);
980 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
981 if (val < 0)
982 return val;
986 val & MDIO_AN_STAT1_ABLE);
1001 int val;
1003 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
1004 if (val < 0)
1005 return val;
1009 val & MDIO_PMA_EXTABLE_10GBLRM);
1012 val & MDIO_PMA_EXTABLE_10GBT);
1015 val & MDIO_PMA_EXTABLE_10GBKX4);
1018 val & MDIO_PMA_EXTABLE_10GBKR);
1021 val & MDIO_PMA_EXTABLE_1000BT);
1024 val & MDIO_PMA_EXTABLE_1000BKX);
1028 val & MDIO_PMA_EXTABLE_100BTX);
1031 val & MDIO_PMA_EXTABLE_100BTX);
1035 val & MDIO_PMA_EXTABLE_10BT);
1038 val & MDIO_PMA_EXTABLE_10BT);
1040 if (val & MDIO_PMA_EXTABLE_NBT) {
1041 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
1043 if (val < 0)
1044 return val;
1048 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
1052 val & MDIO_PMA_NG_EXTABLE_5GBT);
1055 if (val & MDIO_PMA_EXTABLE_BT1) {
1056 val = genphy_c45_pma_baset1_read_abilities(phydev);
1057 if (val < 0)
1058 return val;
1078 int val;
1082 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
1083 if (val < 0)
1084 return val;
1086 if (val & MDIO_AN_STAT1_ABLE)
1091 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
1092 if (val < 0)
1093 return val;
1097 val & MDIO_PMA_STAT2_10GBSR);
1101 val & MDIO_PMA_STAT2_10GBLR);
1105 val & MDIO_PMA_STAT2_10GBER);
1107 if (val & MDIO_PMA_STAT2_EXTABLE) {
1108 val = genphy_c45_pma_read_ext_abilities(phydev);
1109 if (val < 0)
1110 return val;
1342 u16 val = 0;
1372 val = ret;
1376 val = (val & ~MDIO_OATC14_PLCA_NCNT) |
1380 val = (val & ~MDIO_OATC14_PLCA_ID) |
1384 MDIO_OATC14_PLCA_CTRL1, val);
1412 val = ret;
1416 val = (val & ~MDIO_OATC14_PLCA_MAXBC) |
1420 val = (val & ~MDIO_OATC14_PLCA_BTMR) |
1424 MDIO_OATC14_PLCA_BURST, val);