Lines Matching defs:phydev
15 * @phydev: target phy_device struct
17 static bool genphy_c45_baset1_able(struct phy_device *phydev)
21 if (phydev->pma_extable == -ENODATA) {
22 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
26 phydev->pma_extable = val;
29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1);
34 * @phydev: target phy_device struct
36 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev)
40 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);
49 * @phydev: target phy_device struct
51 int genphy_c45_pma_resume(struct phy_device *phydev)
53 if (!genphy_c45_pma_can_sleep(phydev))
56 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
63 * @phydev: target phy_device struct
65 int genphy_c45_pma_suspend(struct phy_device *phydev)
67 if (!genphy_c45_pma_can_sleep(phydev))
70 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
78 * @phydev: target phy_device struct
80 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev)
84 switch (phydev->master_slave_set) {
96 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
100 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
107 * @phydev: target phy_device struct
109 int genphy_c45_pma_setup_forced(struct phy_device *phydev)
114 if (phydev->duplex != DUPLEX_FULL)
117 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
121 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2);
132 switch (phydev->speed) {
134 if (genphy_c45_baset1_able(phydev))
167 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
171 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
175 if (genphy_c45_baset1_able(phydev)) {
176 ret = genphy_c45_pma_baset1_setup_master_slave(phydev);
181 if (phydev->speed == SPEED_1000)
184 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
190 return genphy_c45_an_disable_aneg(phydev);
202 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev)
214 switch (phydev->master_slave_set) {
233 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
237 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising);
239 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L,
246 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising);
248 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M,
260 * @phydev: target phy_device struct
262 * Configure advertisement registers based on modes set in phydev->advertising
267 int genphy_c45_an_config_aneg(struct phy_device *phydev)
272 linkmode_and(phydev->advertising, phydev->advertising,
273 phydev->supported);
275 ret = genphy_c45_an_config_eee_aneg(phydev);
281 if (genphy_c45_baset1_able(phydev))
282 return genphy_c45_baset1_an_config_aneg(phydev);
284 adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
286 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
295 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
297 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
312 * @phydev: target phy_device struct
319 int genphy_c45_an_disable_aneg(struct phy_device *phydev)
323 if (genphy_c45_baset1_able(phydev))
326 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
333 * @phydev: target phy_device struct
339 int genphy_c45_restart_aneg(struct phy_device *phydev)
343 if (genphy_c45_baset1_able(phydev))
346 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg,
353 * @phydev: target phy_device struct
360 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
365 if (genphy_c45_baset1_able(phydev))
370 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
379 return genphy_c45_restart_aneg(phydev);
387 * @phydev: target phy_device struct
396 int genphy_c45_aneg_done(struct phy_device *phydev)
401 if (genphy_c45_baset1_able(phydev))
404 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
412 * @phydev: target phy_device struct
415 * that the link is up, set phydev->link to 1. If an error is encountered,
418 int genphy_c45_read_link(struct phy_device *phydev)
424 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
425 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
433 phydev->link = 0;
447 if (!phy_polling_mode(phydev) || !phydev->link) {
448 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
455 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
463 phydev->link = link;
472 * pause and asym_pause members in phydev.
474 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev)
478 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
483 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising);
484 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0);
485 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0);
487 phydev->pause = 0;
488 phydev->asym_pause = 0;
493 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1);
495 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L);
499 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val);
500 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0;
501 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0;
503 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M);
507 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val);
514 * @phydev: target phy_device struct
518 * in @phydev. This assumes that the auto-negotiation MMD is present, and
522 int genphy_c45_read_lpa(struct phy_device *phydev)
526 if (genphy_c45_baset1_able(phydev))
527 return genphy_c45_baset1_read_lpa(phydev);
529 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
535 phydev->lp_advertising);
536 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
537 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0);
538 phydev->pause = 0;
539 phydev->asym_pause = 0;
544 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising,
548 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
552 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val);
553 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0;
554 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0;
557 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
561 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
570 * @phydev: target phy_device struct
572 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev)
576 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
577 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
579 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL);
584 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
585 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
587 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
588 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
597 * @phydev: target phy_device struct
599 int genphy_c45_read_pma(struct phy_device *phydev)
603 linkmode_zero(phydev->lp_advertising);
605 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
611 phydev->speed = SPEED_10;
614 phydev->speed = SPEED_100;
617 phydev->speed = SPEED_1000;
620 phydev->speed = SPEED_2500;
623 phydev->speed = SPEED_5000;
626 phydev->speed = SPEED_10000;
629 phydev->speed = SPEED_UNKNOWN;
633 phydev->duplex = DUPLEX_FULL;
635 if (genphy_c45_baset1_able(phydev)) {
636 val = genphy_c45_pma_baset1_read_master_slave(phydev);
647 * @phydev: target phy_device struct
649 int genphy_c45_read_mdix(struct phy_device *phydev)
653 if (phydev->speed == SPEED_10000) {
654 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
661 phydev->mdix = ETH_TP_MDI;
665 phydev->mdix = ETH_TP_MDI_X;
669 phydev->mdix = ETH_TP_MDI_INVALID;
680 * @phydev: target phy_device struct
683 int genphy_c45_write_eee_adv(struct phy_device *phydev, unsigned long *adv)
687 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
693 val &= ~phydev->eee_broken_modes;
698 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
710 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) {
716 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
727 phydev->supported_eee)) {
732 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
747 * @phydev: target phy_device struct
750 int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv)
754 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
758 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
765 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) {
769 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
777 phydev->supported_eee)) {
781 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL);
793 * @phydev: target phy_device struct
796 static int genphy_c45_read_eee_lpa(struct phy_device *phydev,
801 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
805 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
812 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) {
816 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE2);
824 phydev->supported_eee)) {
828 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT);
840 * @phydev: target phy_device struct
842 static int genphy_c45_read_eee_cap1(struct phy_device *phydev)
849 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
861 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val);
866 linkmode_and(phydev->supported_eee, phydev->supported_eee,
867 phydev->supported);
874 * @phydev: target phy_device struct
876 static int genphy_c45_read_eee_cap2(struct phy_device *phydev)
883 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2);
891 mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val);
898 * @phydev: target phy_device struct
900 int genphy_c45_read_eee_abilities(struct phy_device *phydev)
908 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) {
909 val = genphy_c45_read_eee_cap1(phydev);
915 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) {
916 val = genphy_c45_read_eee_cap2(phydev);
922 phydev->supported)) {
926 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);
931 phydev->supported_eee,
941 * @phydev: target phy_device struct
943 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev)
945 if (!phydev->eee_enabled) {
948 return genphy_c45_write_eee_adv(phydev, adv);
951 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee);
956 * @phydev: target phy_device struct
960 int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev)
964 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1);
969 phydev->supported,
973 phydev->supported,
977 phydev->supported,
980 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
985 phydev->supported,
994 * @phydev: target phy_device struct
999 int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev)
1003 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
1008 phydev->supported,
1011 phydev->supported,
1014 phydev->supported,
1017 phydev->supported,
1020 phydev->supported,
1023 phydev->supported,
1027 phydev->supported,
1030 phydev->supported,
1034 phydev->supported,
1037 phydev->supported,
1041 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
1047 phydev->supported,
1051 phydev->supported,
1056 val = genphy_c45_pma_baset1_read_abilities(phydev);
1067 * @phydev: target phy_device struct
1076 int genphy_c45_pma_read_abilities(struct phy_device *phydev)
1080 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
1081 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
1082 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
1088 phydev->supported);
1091 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
1096 phydev->supported,
1100 phydev->supported,
1104 phydev->supported,
1108 val = genphy_c45_pma_read_ext_abilities(phydev);
1116 genphy_c45_read_eee_abilities(phydev);
1128 int genphy_c45_baset1_read_status(struct phy_device *phydev)
1133 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1134 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1136 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L);
1140 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M);
1146 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1148 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1151 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED;
1153 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED;
1162 * @phydev: target phy_device struct
1166 int genphy_c45_read_status(struct phy_device *phydev)
1170 ret = genphy_c45_read_link(phydev);
1174 phydev->speed = SPEED_UNKNOWN;
1175 phydev->duplex = DUPLEX_UNKNOWN;
1176 phydev->pause = 0;
1177 phydev->asym_pause = 0;
1179 if (phydev->autoneg == AUTONEG_ENABLE) {
1180 ret = genphy_c45_read_lpa(phydev);
1184 if (genphy_c45_baset1_able(phydev)) {
1185 ret = genphy_c45_baset1_read_status(phydev);
1190 phy_resolve_aneg_linkmode(phydev);
1192 ret = genphy_c45_read_pma(phydev);
1201 * @phydev: target phy_device struct
1207 int genphy_c45_config_aneg(struct phy_device *phydev)
1212 if (phydev->autoneg == AUTONEG_DISABLE)
1213 return genphy_c45_pma_setup_forced(phydev);
1215 ret = genphy_c45_an_config_aneg(phydev);
1221 return genphy_c45_check_and_restart_aneg(phydev, changed);
1227 int gen10g_config_aneg(struct phy_device *phydev)
1233 int genphy_c45_loopback(struct phy_device *phydev, bool enable)
1235 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
1243 * @phydev: target phy_device struct
1251 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable)
1256 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
1259 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) {
1260 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
1265 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2,
1271 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
1278 * @phydev: target phy_device struct
1285 int genphy_c45_plca_get_cfg(struct phy_device *phydev,
1290 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER);
1299 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0);
1305 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1);
1312 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR);
1318 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST);
1331 * @phydev: target phy_device struct
1339 int genphy_c45_plca_set_cfg(struct phy_device *phydev,
1351 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
1366 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1383 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1391 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1406 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1423 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1432 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1446 * @phydev: target phy_device struct
1453 int genphy_c45_plca_get_status(struct phy_device *phydev,
1458 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS);
1469 * @phydev: target phy_device struct
1477 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *adv,
1486 ret = genphy_c45_read_eee_adv(phydev, tmp_adv);
1490 ret = genphy_c45_read_eee_lpa(phydev, tmp_lp);
1497 eee_active = phy_check_valid(phydev->speed, phydev->duplex,
1515 * @phydev: target phy_device struct
1521 int genphy_c45_ethtool_get_eee(struct phy_device *phydev,
1529 ret = genphy_c45_eee_is_active(phydev, adv, lp, &is_enabled);
1535 linkmode_copy(data->supported, phydev->supported_eee);
1545 * @phydev: target phy_device struct
1556 int genphy_c45_ethtool_set_eee(struct phy_device *phydev,
1567 if (linkmode_andnot(tmp, adv, phydev->supported_eee)) {
1568 phydev_warn(phydev, "At least some EEE link modes are not supported.\n");
1572 adv = phydev->supported_eee;
1575 linkmode_copy(phydev->advertising_eee, adv);
1578 phydev->eee_enabled = data->eee_enabled;
1580 ret = genphy_c45_an_config_eee_aneg(phydev);
1582 ret = phy_restart_aneg(phydev);