Lines Matching defs:phydev
276 void (*counters_enable)(struct phy_device *phydev);
280 void (*ptp_init)(struct phy_device *phydev);
281 void (*ptp_enable)(struct phy_device *phydev, bool enable);
282 void (*nmi_handler)(struct phy_device *phydev,
287 struct nxp_c45_phy_data *nxp_c45_get_data(struct phy_device *phydev)
289 return phydev->drv->driver_data;
293 struct nxp_c45_regmap *nxp_c45_get_regmap(struct phy_device *phydev)
295 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev);
300 static int nxp_c45_read_reg_field(struct phy_device *phydev,
307 phydev_err(phydev, "Trying to read a reg field of size 0.\n");
311 ret = phy_read_mmd(phydev, reg_field->devad, reg_field->reg);
324 static int nxp_c45_write_reg_field(struct phy_device *phydev,
332 phydev_err(phydev, "Trying to write a reg field of size 0.\n");
341 return phy_modify_mmd_changed(phydev, reg_field->devad,
345 static int nxp_c45_set_reg_field(struct phy_device *phydev,
349 phydev_err(phydev, "Trying to set a reg field of size different than 1.\n");
353 return nxp_c45_write_reg_field(phydev, reg_field, 1);
356 static int nxp_c45_clear_reg_field(struct phy_device *phydev,
360 phydev_err(phydev, "Trying to set a reg field of size different than 1.\n");
364 return nxp_c45_write_reg_field(phydev, reg_field, 0);
367 static bool nxp_c45_poll_txts(struct phy_device *phydev)
369 return phydev->irq <= 0;
377 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
379 nxp_c45_set_reg_field(priv->phydev, ®map->ltc_read);
380 ts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
382 ts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
384 ts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
386 ts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
409 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
411 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_0,
413 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_1,
415 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_0,
417 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_1,
419 nxp_c45_set_reg_field(priv->phydev, ®map->ltc_write);
439 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev);
451 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1,
459 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1,
504 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
506 extts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
508 extts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
510 extts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
512 extts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
514 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1,
520 static bool tja1120_extts_is_valid(struct phy_device *phydev)
525 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1,
535 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
536 struct phy_device *phydev = priv->phydev;
541 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1,
545 valid = tja1120_extts_is_valid(phydev);
553 phy_write_mmd(phydev, MDIO_MMD_VEND1,
555 valid = tja1120_extts_is_valid(phydev);
568 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
569 struct phy_device *phydev = priv->phydev;
572 nxp_c45_read_reg_field(phydev, ®map->domain_number);
574 nxp_c45_read_reg_field(phydev, ®map->msg_type);
576 nxp_c45_read_reg_field(phydev, ®map->sequence_id);
578 nxp_c45_read_reg_field(phydev, ®map->nsec_15_0);
580 nxp_c45_read_reg_field(phydev, ®map->nsec_29_16) << 16;
581 hwts->sec = nxp_c45_read_reg_field(phydev, ®map->sec_1_0);
582 hwts->sec |= nxp_c45_read_reg_field(phydev, ®map->sec_4_2) << 2;
592 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL,
594 reg = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_DATA_0);
605 static bool tja1120_egress_ts_is_valid(struct phy_device *phydev)
610 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S);
619 struct phy_device *phydev = priv->phydev;
625 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_END);
627 valid = tja1120_egress_ts_is_valid(phydev);
635 phy_write_mmd(phydev, MDIO_MMD_VEND1,
637 valid = tja1120_egress_ts_is_valid(phydev);
642 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S,
679 phydev_warn(priv->phydev,
687 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev);
688 bool poll_txts = nxp_c45_poll_txts(priv->phydev);
739 struct phy_device *phydev = priv->phydev;
741 phy_write_mmd(phydev, MDIO_MMD_VEND1,
748 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
749 struct phy_device *phydev = priv->phydev;
760 nxp_c45_clear_reg_field(priv->phydev,
762 nxp_c45_clear_reg_field(priv->phydev,
775 phydev_warn(phydev, "The period can be set only to 1 second.");
781 phydev_warn(phydev, "The start time is not configurable. Should be set to 0 seconds and 0 nanoseconds.");
787 phydev_warn(phydev, "The phase can be set only to 0 or 500000000 nanoseconds.");
792 nxp_c45_clear_reg_field(priv->phydev,
795 nxp_c45_set_reg_field(priv->phydev,
801 nxp_c45_set_reg_field(priv->phydev, ®map->pps_enable);
806 static void nxp_c45_set_rising_or_falling(struct phy_device *phydev,
810 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
814 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
818 static void nxp_c45_set_rising_and_falling(struct phy_device *phydev,
826 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
830 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
835 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
839 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
847 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev);
874 nxp_c45_set_rising_and_falling(priv->phydev, extts);
876 nxp_c45_set_rising_or_falling(priv->phydev, extts);
954 &priv->phydev->mdio.dev);
977 if (nxp_c45_poll_txts(priv->phydev))
1013 struct phy_device *phydev = priv->phydev;
1019 data = nxp_c45_get_data(phydev);
1037 phy_write_mmd(phydev, MDIO_MMD_VEND1,
1040 data->ptp_enable(phydev, true);
1042 phy_write_mmd(phydev, MDIO_MMD_VEND1,
1045 data->ptp_enable(phydev, false);
1048 if (nxp_c45_poll_txts(priv->phydev))
1052 nxp_c45_set_reg_field(phydev, &data->regmap->irq_egr_ts_en);
1054 nxp_c45_clear_reg_field(phydev, &data->regmap->irq_egr_ts_en);
1124 static int nxp_c45_get_sset_count(struct phy_device *phydev)
1126 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev);
1131 static void nxp_c45_get_strings(struct phy_device *phydev, u8 *data)
1133 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev);
1134 size_t count = nxp_c45_get_sset_count(phydev);
1150 static void nxp_c45_get_stats(struct phy_device *phydev,
1153 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev);
1154 size_t count = nxp_c45_get_sset_count(phydev);
1168 ret = nxp_c45_read_reg_field(phydev, reg_field);
1176 static int nxp_c45_config_enable(struct phy_device *phydev)
1178 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL,
1183 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL,
1185 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL,
1187 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL,
1193 static int nxp_c45_start_op(struct phy_device *phydev)
1195 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL,
1199 static int nxp_c45_config_intr(struct phy_device *phydev)
1203 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1204 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1209 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1213 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1218 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1222 static int tja1103_config_intr(struct phy_device *phydev)
1227 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_ALWAYS_ACCESSIBLE,
1232 return nxp_c45_config_intr(phydev);
1235 static int tja1120_config_intr(struct phy_device *phydev)
1239 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1240 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1244 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1250 return nxp_c45_config_intr(phydev);
1253 static irqreturn_t nxp_c45_handle_interrupt(struct phy_device *phydev)
1255 const struct nxp_c45_phy_data *data = nxp_c45_get_data(phydev);
1256 struct nxp_c45_phy *priv = phydev->priv;
1261 irq = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_STATUS);
1263 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_ACK,
1265 phy_trigger_machine(phydev);
1269 irq = nxp_c45_read_reg_field(phydev, &data->regmap->irq_egr_ts_status);
1276 phy_write_mmd(phydev, MDIO_MMD_VEND1,
1284 data->nmi_handler(phydev, &ret);
1285 nxp_c45_handle_macsec_interrupt(phydev, &ret);
1290 static int nxp_c45_soft_reset(struct phy_device *phydev)
1294 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL,
1299 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
1305 static int nxp_c45_cable_test_start(struct phy_device *phydev)
1307 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(phydev);
1309 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1311 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test,
1315 static int nxp_c45_cable_test_get_status(struct phy_device *phydev,
1318 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(phydev);
1322 ret = nxp_c45_read_reg_field(phydev, ®map->cable_test_valid);
1329 cable_test_result = nxp_c45_read_reg_field(phydev,
1334 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1338 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1342 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1346 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1350 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test,
1352 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1355 return nxp_c45_start_op(phydev);
1358 static int nxp_c45_get_sqi(struct phy_device *phydev)
1362 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_SIGNAL_QUALITY);
1371 static void tja1120_link_change_notify(struct phy_device *phydev)
1376 if (phydev->state == PHY_NOLINK) {
1377 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1379 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1384 static int nxp_c45_get_sqi_max(struct phy_device *phydev)
1389 static int nxp_c45_check_delay(struct phy_device *phydev, u32 delay)
1392 phydev_err(phydev, "delay value smaller than %u\n", MIN_ID_PS);
1397 phydev_err(phydev, "delay value higher than %u\n", MAX_ID_PS);
1404 static void nxp_c45_counters_enable(struct phy_device *phydev)
1406 const struct nxp_c45_phy_data *data = nxp_c45_get_data(phydev);
1408 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_LINK_DROP_COUNTER,
1411 data->counters_enable(phydev);
1414 static void nxp_c45_ptp_init(struct phy_device *phydev)
1416 const struct nxp_c45_phy_data *data = nxp_c45_get_data(phydev);
1418 phy_write_mmd(phydev, MDIO_MMD_VEND1,
1421 nxp_c45_clear_reg_field(phydev, &data->regmap->ltc_lock_ctrl);
1423 data->ptp_init(phydev);
1437 static void nxp_c45_disable_delays(struct phy_device *phydev)
1439 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, ID_ENABLE);
1440 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, ID_ENABLE);
1443 static void nxp_c45_set_delays(struct phy_device *phydev)
1445 struct nxp_c45_phy *priv = phydev->priv;
1450 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1451 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
1453 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID,
1456 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID,
1460 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1461 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
1463 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID,
1466 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID,
1471 static int nxp_c45_get_delays(struct phy_device *phydev)
1473 struct nxp_c45_phy *priv = phydev->priv;
1476 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1477 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
1478 ret = device_property_read_u32(&phydev->mdio.dev,
1484 ret = nxp_c45_check_delay(phydev, priv->tx_delay);
1486 phydev_err(phydev,
1492 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1493 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
1494 ret = device_property_read_u32(&phydev->mdio.dev,
1500 ret = nxp_c45_check_delay(phydev, priv->rx_delay);
1502 phydev_err(phydev,
1511 static int nxp_c45_set_phy_mode(struct phy_device *phydev)
1515 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES);
1516 phydev_dbg(phydev, "Clause 45 managed PHY abilities 0x%x\n", ret);
1518 switch (phydev->interface) {
1521 phydev_err(phydev, "rgmii mode not supported\n");
1524 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
1526 nxp_c45_disable_delays(phydev);
1532 phydev_err(phydev, "rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n");
1535 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
1537 ret = nxp_c45_get_delays(phydev);
1541 nxp_c45_set_delays(phydev);
1545 phydev_err(phydev, "mii mode not supported\n");
1548 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
1553 phydev_err(phydev, "rev-mii mode not supported\n");
1556 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
1561 phydev_err(phydev, "rmii mode not supported\n");
1564 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
1569 phydev_err(phydev, "sgmii mode not supported\n");
1572 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
1584 static int nxp_c45_config_init(struct phy_device *phydev)
1588 ret = nxp_c45_config_enable(phydev);
1590 phydev_err(phydev, "Failed to enable config\n");
1597 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1);
1598 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2);
1600 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG,
1603 ret = nxp_c45_set_phy_mode(phydev);
1607 phydev->autoneg = AUTONEG_DISABLE;
1609 nxp_c45_counters_enable(phydev);
1610 nxp_c45_ptp_init(phydev);
1611 ret = nxp_c45_macsec_config_init(phydev);
1615 return nxp_c45_start_op(phydev);
1618 static int nxp_c45_get_features(struct phy_device *phydev)
1620 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported);
1621 linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, phydev->supported);
1623 return genphy_c45_pma_read_abilities(phydev);
1626 static int nxp_c45_probe(struct phy_device *phydev)
1634 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1641 priv->phydev = phydev;
1643 phydev->priv = priv;
1647 phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1651 phydev_dbg(phydev, "the phy does not support PTP");
1661 phydev->mii_ts = &priv->mii_ts;
1664 phydev_dbg(phydev, "PTP support not enabled even if the phy supports it");
1670 phydev_info(phydev, "the phy does not support MACsec\n");
1675 ret = nxp_c45_macsec_probe(phydev);
1676 phydev_dbg(phydev, "MACsec support enabled.");
1678 phydev_dbg(phydev, "MACsec support not enabled even if the phy supports it");
1686 static void nxp_c45_remove(struct phy_device *phydev)
1688 struct nxp_c45_phy *priv = phydev->priv;
1695 nxp_c45_macsec_remove(phydev);
1698 static void tja1103_counters_enable(struct phy_device *phydev)
1700 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_PREAMBLE_COUNT,
1702 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_PREAMBLE_COUNT,
1704 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_IPG_LENGTH,
1706 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_IPG_LENGTH,
1710 static void tja1103_ptp_init(struct phy_device *phydev)
1712 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_TS_INSRT_CTRL,
1714 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES,
1718 static void tja1103_ptp_enable(struct phy_device *phydev, bool enable)
1721 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1725 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1730 static void tja1103_nmi_handler(struct phy_device *phydev,
1735 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1738 phy_write_mmd(phydev, MDIO_MMD_VEND1,
1813 static void tja1120_counters_enable(struct phy_device *phydev)
1815 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_SYMBOL_ERROR_CNT_XTD,
1817 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_STATUS,
1819 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_CONFIG,
1823 static void tja1120_ptp_init(struct phy_device *phydev)
1825 phy_write_mmd(phydev, MDIO_MMD_VEND1, TJA1120_RX_TS_INSRT_CTRL,
1827 phy_write_mmd(phydev, MDIO_MMD_VEND1, TJA1120_VEND1_EXT_TS_MODE,
1829 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONFIG,
1833 static void tja1120_ptp_enable(struct phy_device *phydev, bool enable)
1836 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1840 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1845 static void tja1120_nmi_handler(struct phy_device *phydev,
1850 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1853 phy_write_mmd(phydev, MDIO_MMD_VEND1,