Lines Matching defs:phydev
290 static int nxp_c45_macsec_write(struct phy_device *phydev, u16 addr, u32 value)
298 phydev_dbg(phydev, "write addr 0x%x value 0x%x\n", addr, value);
301 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, laddr, lvalue);
307 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, laddr, lvalue);
312 static int nxp_c45_macsec_read(struct phy_device *phydev, u16 addr, u32 *value)
321 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, laddr);
327 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, laddr);
334 phydev_dbg(phydev, "read addr 0x%x value 0x%x\n", addr, *value);
339 static void nxp_c45_macsec_read32_64(struct phy_device *phydev, u16 addr,
344 nxp_c45_macsec_read(phydev, addr, &lvalue);
348 static void nxp_c45_macsec_read64(struct phy_device *phydev, u16 addr,
353 nxp_c45_macsec_read(phydev, addr, &lvalue);
355 nxp_c45_macsec_read(phydev, addr + 4, &lvalue);
359 static void nxp_c45_secy_irq_en(struct phy_device *phydev,
364 nxp_c45_macsec_read(phydev, MACSEC_EVER, ®);
369 nxp_c45_macsec_write(phydev, MACSEC_EVER, reg);
466 static void nxp_c45_sa_set_pn(struct phy_device *phydev,
474 nxp_c45_macsec_write(phydev, sa_regs->npn, npn.lower);
475 nxp_c45_macsec_write(phydev, sa_regs->xnpn, npn.upper);
484 nxp_c45_macsec_write(phydev, sa_regs->lnpn, lnpn.lower);
485 nxp_c45_macsec_write(phydev, sa_regs->lxnpn, lnpn.upper);
492 struct phy_device *phydev = ctx->phydev;
503 nxp_c45_macsec_write(phydev, reg, value);
510 nxp_c45_macsec_write(phydev, reg, value);
514 nxp_c45_macsec_write(phydev, sa_regs->ssci, value);
517 nxp_c45_macsec_write(phydev, sa_regs->cs, MACSEC_SA_CS_A);
520 static void nxp_c45_rx_sa_clear_stats(struct phy_device *phydev,
523 nxp_c45_macsec_write(phydev, sa->regs->ipis, 0);
524 nxp_c45_macsec_write(phydev, sa->regs->ipnvs, 0);
525 nxp_c45_macsec_write(phydev, sa->regs->ipos, 0);
527 nxp_c45_macsec_write(phydev, MACSEC_RXAN0INUSS + sa->an * 4, 0);
528 nxp_c45_macsec_write(phydev, MACSEC_RXAN0IPUSS + sa->an * 4, 0);
531 static void nxp_c45_rx_sa_read_stats(struct phy_device *phydev,
535 nxp_c45_macsec_read(phydev, sa->regs->ipis, &stats->InPktsInvalid);
536 nxp_c45_macsec_read(phydev, sa->regs->ipnvs, &stats->InPktsNotValid);
537 nxp_c45_macsec_read(phydev, sa->regs->ipos, &stats->InPktsOK);
540 static void nxp_c45_tx_sa_clear_stats(struct phy_device *phydev,
543 nxp_c45_macsec_write(phydev, sa->regs->opps, 0);
544 nxp_c45_macsec_write(phydev, sa->regs->opes, 0);
547 static void nxp_c45_tx_sa_read_stats(struct phy_device *phydev,
551 nxp_c45_macsec_read(phydev, sa->regs->opps, &stats->OutPktsProtected);
552 nxp_c45_macsec_read(phydev, sa->regs->opes, &stats->OutPktsEncrypted);
555 static void nxp_c45_rx_sa_update(struct phy_device *phydev,
563 nxp_c45_macsec_write(phydev, sa_regs->cs, cfg);
566 static void nxp_c45_tx_sa_update(struct phy_device *phydev,
571 nxp_c45_macsec_read(phydev, MACSEC_TXSC_CFG, &cfg);
586 nxp_c45_macsec_write(phydev, MACSEC_TXSC_CFG, cfg);
589 static void nxp_c45_set_sci(struct phy_device *phydev, u16 sci_base_addr,
594 nxp_c45_macsec_write(phydev, sci_base_addr, lsci >> 32);
595 nxp_c45_macsec_write(phydev, sci_base_addr + 4, lsci);
605 static void nxp_c45_select_secy(struct phy_device *phydev, u8 id)
607 nxp_c45_macsec_write(phydev, MACSEC_RXSCA, id);
608 nxp_c45_macsec_write(phydev, MACSEC_RXSCKA, id);
609 nxp_c45_macsec_write(phydev, MACSEC_TXSCA, id);
610 nxp_c45_macsec_write(phydev, MACSEC_TXSCKA, id);
654 struct nxp_c45_phy *priv = ctx->phydev->priv;
669 static void nxp_c45_tx_sc_en_flt(struct phy_device *phydev, int secy_id,
675 nxp_c45_macsec_read(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), ®);
680 nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), reg);
683 static void nxp_c45_tx_sc_set_flt(struct phy_device *phydev,
691 nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_DA_SA(tx_flt_base), reg);
695 nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_SA(tx_flt_base), reg);
696 nxp_c45_macsec_read(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), ®);
699 nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), reg);
702 static void nxp_c45_tx_sc_update(struct phy_device *phydev,
707 nxp_c45_macsec_read(phydev, MACSEC_TXSC_CFG, &cfg);
709 phydev_dbg(phydev, "XPN %s\n", phy_secy->secy->xpn ? "on" : "off");
715 phydev_dbg(phydev, "key len %u\n", phy_secy->secy->key_len);
721 phydev_dbg(phydev, "encryption %s\n",
728 phydev_dbg(phydev, "protect frames %s\n",
735 phydev_dbg(phydev, "send sci %s\n",
742 phydev_dbg(phydev, "end station %s\n",
749 phydev_dbg(phydev, "scb %s\n",
756 nxp_c45_macsec_write(phydev, MACSEC_TXSC_CFG, cfg);
759 static void nxp_c45_tx_sc_clear_stats(struct phy_device *phydev,
766 nxp_c45_tx_sa_clear_stats(phydev, pos);
768 nxp_c45_macsec_write(phydev, MACSEC_OPUS, 0);
769 nxp_c45_macsec_write(phydev, MACSEC_OPTLS, 0);
770 nxp_c45_macsec_write(phydev, MACSEC_OOP1HS, 0);
771 nxp_c45_macsec_write(phydev, MACSEC_OOP2HS, 0);
772 nxp_c45_macsec_write(phydev, MACSEC_OOE1HS, 0);
773 nxp_c45_macsec_write(phydev, MACSEC_OOE2HS, 0);
776 static void nxp_c45_set_rx_sc0_impl(struct phy_device *phydev,
781 nxp_c45_macsec_read(phydev, MACSEC_CFG, ®);
786 nxp_c45_macsec_write(phydev, MACSEC_CFG, reg);
800 static void nxp_c45_rx_sc_en(struct phy_device *phydev,
805 nxp_c45_macsec_read(phydev, MACSEC_RXSC_CFG, ®);
810 nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, reg);
813 static void nxp_c45_rx_sc_update(struct phy_device *phydev,
817 struct nxp_c45_phy *priv = phydev->priv;
820 nxp_c45_macsec_read(phydev, MACSEC_RXSC_CFG, &cfg);
824 phydev_dbg(phydev, "validate frames %u\n",
826 phydev_dbg(phydev, "replay_protect %s window %u\n",
831 nxp_c45_macsec_write(phydev, MACSEC_RPW,
837 phydev_dbg(phydev, "rx_sc->active %s\n",
845 phydev_dbg(phydev, "key len %u\n", phy_secy->secy->key_len);
851 phydev_dbg(phydev, "XPN %s\n", phy_secy->secy->xpn ? "on" : "off");
857 nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, cfg);
860 static void nxp_c45_rx_sc_clear_stats(struct phy_device *phydev,
868 nxp_c45_rx_sa_clear_stats(phydev, pos);
870 nxp_c45_macsec_write(phydev, MACSEC_INOD1HS, 0);
871 nxp_c45_macsec_write(phydev, MACSEC_INOD2HS, 0);
873 nxp_c45_macsec_write(phydev, MACSEC_INOV1HS, 0);
874 nxp_c45_macsec_write(phydev, MACSEC_INOV2HS, 0);
876 nxp_c45_macsec_write(phydev, MACSEC_RXSCIPDS, 0);
877 nxp_c45_macsec_write(phydev, MACSEC_RXSCIPLS, 0);
878 nxp_c45_macsec_write(phydev, MACSEC_RXSCIPUS, 0);
881 nxp_c45_macsec_write(phydev, MACSEC_RXAN0INUSS + i * 4, 0);
882 nxp_c45_macsec_write(phydev, MACSEC_RXAN0IPUSS + i * 4, 0);
886 static void nxp_c45_rx_sc_del(struct phy_device *phydev,
891 nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, 0);
892 nxp_c45_macsec_write(phydev, MACSEC_RPW, 0);
893 nxp_c45_set_sci(phydev, MACSEC_RXSC_SCI_1H, 0);
895 nxp_c45_rx_sc_clear_stats(phydev, phy_secy);
899 nxp_c45_rx_sa_update(phydev, pos, false);
905 static void nxp_c45_clear_global_stats(struct phy_device *phydev)
907 nxp_c45_macsec_write(phydev, MACSEC_INPBTS, 0);
908 nxp_c45_macsec_write(phydev, MACSEC_INPWTS, 0);
909 nxp_c45_macsec_write(phydev, MACSEC_IPSNFS, 0);
912 static void nxp_c45_macsec_en(struct phy_device *phydev, bool en)
916 nxp_c45_macsec_read(phydev, MACSEC_CFG, ®);
921 nxp_c45_macsec_write(phydev, MACSEC_CFG, reg);
926 struct phy_device *phydev = ctx->phydev;
927 struct nxp_c45_phy *priv = phydev->priv;
935 nxp_c45_select_secy(phydev, phy_secy->secy_id);
937 nxp_c45_tx_sc_en_flt(phydev, phy_secy->secy_id, true);
938 nxp_c45_set_rx_sc0_impl(phydev, phy_secy->rx_sc0_impl);
940 nxp_c45_rx_sc_en(phydev, phy_secy->rx_sc, true);
944 nxp_c45_macsec_en(phydev, true);
953 struct phy_device *phydev = ctx->phydev;
954 struct nxp_c45_phy *priv = phydev->priv;
962 nxp_c45_select_secy(phydev, phy_secy->secy_id);
964 nxp_c45_tx_sc_en_flt(phydev, phy_secy->secy_id, false);
966 nxp_c45_rx_sc_en(phydev, phy_secy->rx_sc, false);
967 nxp_c45_set_rx_sc0_impl(phydev, false);
972 nxp_c45_macsec_en(phydev, false);
979 struct phy_device *phydev = ctx->phydev;
980 struct nxp_c45_phy *priv = phydev->priv;
985 phydev_dbg(phydev, "add SecY SCI %016llx\n",
1017 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1018 nxp_c45_set_sci(phydev, MACSEC_TXSC_SCI_1H, ctx->secy->sci);
1019 nxp_c45_tx_sc_set_flt(phydev, phy_secy);
1020 nxp_c45_tx_sc_update(phydev, phy_secy);
1021 if (phy_interrupt_is_valid(phydev))
1022 nxp_c45_secy_irq_en(phydev, phy_secy, true);
1047 struct phy_device *phydev = ctx->phydev;
1048 struct nxp_c45_phy *priv = phydev->priv;
1053 phydev_dbg(phydev, "update SecY SCI %016llx\n",
1071 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1072 nxp_c45_tx_sc_set_flt(phydev, phy_secy);
1073 nxp_c45_tx_sc_update(phydev, phy_secy);
1075 nxp_c45_tx_sa_update(phydev, &next_sa, ctx->secy->operational);
1077 nxp_c45_set_rx_sc0_impl(phydev, phy_secy->rx_sc0_impl);
1079 nxp_c45_rx_sc_update(phydev, phy_secy);
1087 struct phy_device *phydev = ctx->phydev;
1088 struct nxp_c45_phy *priv = phydev->priv;
1092 phydev_dbg(phydev, "delete SecY SCI %016llx\n",
1098 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1102 nxp_c45_tx_sa_update(phydev, &next_sa, false);
1103 nxp_c45_tx_sc_clear_stats(phydev, phy_secy);
1105 nxp_c45_rx_sc_del(phydev, phy_secy);
1108 if (phy_interrupt_is_valid(phydev))
1109 nxp_c45_secy_irq_en(phydev, phy_secy, false);
1115 nxp_c45_clear_global_stats(phydev);
1122 struct phy_device *phydev = ctx->phydev;
1123 struct nxp_c45_phy *priv = phydev->priv;
1126 phydev_dbg(phydev, "add RX SC SCI %016llx %s\n",
1143 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1144 nxp_c45_set_sci(phydev, MACSEC_RXSC_SCI_1H, ctx->rx_sc->sci);
1145 nxp_c45_rx_sc_update(phydev, phy_secy);
1152 struct phy_device *phydev = ctx->phydev;
1153 struct nxp_c45_phy *priv = phydev->priv;
1156 phydev_dbg(phydev, "update RX SC SCI %016llx %s\n",
1164 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1165 nxp_c45_rx_sc_update(phydev, phy_secy);
1172 struct phy_device *phydev = ctx->phydev;
1173 struct nxp_c45_phy *priv = phydev->priv;
1176 phydev_dbg(phydev, "delete RX SC SCI %016llx %s\n",
1184 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1185 nxp_c45_rx_sc_del(phydev, phy_secy);
1194 struct phy_device *phydev = ctx->phydev;
1195 struct nxp_c45_phy *priv = phydev->priv;
1200 phydev_dbg(phydev, "add RX SA %u %s to RX SC SCI %016llx\n",
1212 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1213 nxp_c45_sa_set_pn(phydev, sa, rx_sa->next_pn,
1216 nxp_c45_rx_sa_update(phydev, sa, rx_sa->active);
1224 struct phy_device *phydev = ctx->phydev;
1225 struct nxp_c45_phy *priv = phydev->priv;
1230 phydev_dbg(phydev, "update RX SA %u %s to RX SC SCI %016llx\n",
1242 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1244 nxp_c45_sa_set_pn(phydev, sa, rx_sa->next_pn,
1246 nxp_c45_rx_sa_update(phydev, sa, rx_sa->active);
1254 struct phy_device *phydev = ctx->phydev;
1255 struct nxp_c45_phy *priv = phydev->priv;
1260 phydev_dbg(phydev, "delete RX SA %u %s to RX SC SCI %016llx\n",
1272 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1273 nxp_c45_rx_sa_update(phydev, sa, false);
1274 nxp_c45_rx_sa_clear_stats(phydev, sa);
1284 struct phy_device *phydev = ctx->phydev;
1285 struct nxp_c45_phy *priv = phydev->priv;
1290 phydev_dbg(phydev, "add TX SA %u %s to TX SC %016llx\n",
1302 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1303 nxp_c45_sa_set_pn(phydev, sa, tx_sa->next_pn, 0);
1306 nxp_c45_tx_sa_update(phydev, sa, tx_sa->active);
1314 struct phy_device *phydev = ctx->phydev;
1315 struct nxp_c45_phy *priv = phydev->priv;
1320 phydev_dbg(phydev, "update TX SA %u %s to TX SC %016llx\n",
1332 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1334 nxp_c45_sa_set_pn(phydev, sa, tx_sa->next_pn, 0);
1336 nxp_c45_tx_sa_update(phydev, sa, tx_sa->active);
1343 struct phy_device *phydev = ctx->phydev;
1344 struct nxp_c45_phy *priv = phydev->priv;
1349 phydev_dbg(phydev, "delete TX SA %u %s to TX SC %016llx\n",
1361 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1363 nxp_c45_tx_sa_update(phydev, sa, false);
1364 nxp_c45_tx_sa_clear_stats(phydev, sa);
1373 struct phy_device *phydev = ctx->phydev;
1374 struct nxp_c45_phy *priv = phydev->priv;
1383 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1385 nxp_c45_macsec_read32_64(phydev, MACSEC_OPUS,
1387 nxp_c45_macsec_read32_64(phydev, MACSEC_OPTLS,
1389 nxp_c45_macsec_read32_64(phydev, MACSEC_INPBTS,
1393 nxp_c45_macsec_read32_64(phydev, MACSEC_INPWTS,
1396 nxp_c45_macsec_read32_64(phydev, MACSEC_INPWTS,
1400 nxp_c45_macsec_read32_64(phydev, MACSEC_IPSNFS,
1403 nxp_c45_macsec_read32_64(phydev, MACSEC_IPSNFS,
1414 struct phy_device *phydev = ctx->phydev;
1415 struct nxp_c45_phy *priv = phydev->priv;
1426 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1428 nxp_c45_macsec_read64(phydev, MACSEC_OOE1HS,
1430 nxp_c45_macsec_read64(phydev, MACSEC_OOP1HS,
1437 nxp_c45_tx_sa_read_stats(phydev, pos, &tx_sa_stats);
1448 struct phy_device *phydev = ctx->phydev;
1449 struct nxp_c45_phy *priv = phydev->priv;
1464 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1465 nxp_c45_tx_sa_read_stats(phydev, sa, stats);
1472 struct phy_device *phydev = ctx->phydev;
1473 struct nxp_c45_phy *priv = phydev->priv;
1489 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1496 nxp_c45_rx_sa_read_stats(phydev, pos, &rx_sa_stats);
1504 nxp_c45_macsec_read(phydev, MACSEC_RXAN0INUSS + i * 4, ®);
1506 nxp_c45_macsec_read(phydev, MACSEC_RXAN0IPUSS + i * 4, ®);
1510 nxp_c45_macsec_read64(phydev, MACSEC_INOD1HS,
1512 nxp_c45_macsec_read64(phydev, MACSEC_INOV1HS,
1515 nxp_c45_macsec_read32_64(phydev, MACSEC_RXSCIPDS,
1517 nxp_c45_macsec_read32_64(phydev, MACSEC_RXSCIPLS,
1519 nxp_c45_macsec_read32_64(phydev, MACSEC_RXSCIPUS,
1527 struct phy_device *phydev = ctx->phydev;
1528 struct nxp_c45_phy *priv = phydev->priv;
1543 nxp_c45_select_secy(phydev, phy_secy->secy_id);
1545 nxp_c45_rx_sa_read_stats(phydev, sa, stats);
1546 nxp_c45_macsec_read(phydev, MACSEC_RXAN0INUSS + an * 4,
1548 nxp_c45_macsec_read(phydev, MACSEC_RXAN0IPUSS + an * 4,
1561 static int nxp_c45_mdo_insert_tx_tag(struct phy_device *phydev,
1604 int nxp_c45_macsec_config_init(struct phy_device *phydev)
1606 struct nxp_c45_phy *priv = phydev->priv;
1612 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES,
1617 ret = nxp_c45_macsec_write(phydev, ADPTR_CNTRL, ADPTR_CNTRL_CONFIG_EN |
1622 ret = nxp_c45_macsec_write(phydev, ADPTR_TX_TAG_CNTRL,
1627 ret = nxp_c45_macsec_write(phydev, ADPTR_CNTRL, ADPTR_CNTRL_ADPTR_EN);
1631 ret = nxp_c45_macsec_write(phydev, MACSEC_TPNET, PN_WRAP_THRESHOLD);
1636 ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0D2, ETH_P_PAE);
1640 ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0M1, MACSEC_OVP);
1644 ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0M2, ETYPE_MASK);
1648 ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0R, MACSEC_UPFR_EN);
1653 int nxp_c45_macsec_probe(struct phy_device *phydev)
1655 struct nxp_c45_phy *priv = phydev->priv;
1656 struct device *dev = &phydev->mdio.dev;
1663 phydev->macsec_ops = &nxp_c45_macsec_ops;
1668 void nxp_c45_macsec_remove(struct phy_device *phydev)
1670 struct nxp_c45_phy *priv = phydev->priv;
1679 nxp_c45_macsec_en(phydev, false);
1688 void nxp_c45_handle_macsec_interrupt(struct phy_device *phydev,
1691 struct nxp_c45_phy *priv = phydev->priv;
1702 nxp_c45_macsec_read(phydev, MACSEC_EVR, ®);
1715 phydev_dbg(phydev, "pn_wrapped: TX SC %d, encoding_sa %u\n",
1725 nxp_c45_macsec_write(phydev, MACSEC_EVR,