net/phy/national.c

52 static u8 ns_exp_read(struct phy_device *phydev, u16 reg)
54 	phy_write(phydev, NS_EXP_MEM_ADD, reg);
55 	return phy_read(phydev, NS_EXP_MEM_DATA);
58 static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data)
60 	phy_write(phydev, NS_EXP_MEM_ADD, reg);
61 	phy_write(phydev, NS_EXP_MEM_DATA, data);
64 static int ns_ack_interrupt(struct phy_device *phydev)
66 	int ret = phy_read(phydev, DP83865_INT_STATUS);
73 	ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
78 static irqreturn_t ns_handle_interrupt(struct phy_device *phydev)
82 	irq_status = phy_read(phydev, DP83865_INT_STATUS);
84 		phy_error(phydev);
92 	phy_write(phydev, DP83865_INT_CLEAR, irq_status & ~0x7);
94 	phy_trigger_machine(phydev);
99 static int ns_config_intr(struct phy_device *phydev)
103 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
104 		err = ns_ack_interrupt(phydev);
108 		err = phy_write(phydev, DP83865_INT_MASK,
111 		err = phy_write(phydev, DP83865_INT_MASK, 0);
115 		err = ns_ack_interrupt(phydev);
121 static void ns_giga_speed_fallback(struct phy_device *phydev, int mode)
123 	int bmcr = phy_read(phydev, MII_BMCR);
125 	phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
128 	phy_write(phydev, NS_EXP_MEM_CTL, 0);
129 	phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0);
130 	phy_write(phydev, NS_EXP_MEM_DATA, 0x0008);
131 	phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN));
132 	phy_write(phydev, LED_CTRL_REG, mode);
135 static void ns_10_base_t_hdx_loopack(struct phy_device *phydev, int disable)
140 		ns_exp_write(phydev, 0x1c0,
141 			     ns_exp_read(phydev, 0x1c0) | lb_dis);
143 		ns_exp_write(phydev, 0x1c0,
144 			     ns_exp_read(phydev, 0x1c0) & ~lb_dis);
147 		 (ns_exp_read(phydev, 0x1c0) & lb_dis) ? "off" : "on");
150 static int ns_config_init(struct phy_device *phydev)
152 	ns_giga_speed_fallback(phydev, ALL_FALLBACK_ON);
156 	ns_10_base_t_hdx_loopack(phydev, hdx_loopback_off);
157 	return ns_ack_interrupt(phydev);