net/phy/mxl-gpy.c

163 	struct phy_device *phydev = dev_get_drvdata(dev);
166 	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA);
200 static int gpy_hwmon_register(struct phy_device *phydev)
202 	struct device *dev = &phydev->mdio.dev;
211 							 phydev,
218 static int gpy_hwmon_register(struct phy_device *phydev)
224 static int gpy_mbox_read(struct phy_device *phydev, u32 addr)
226 	struct gpy_priv *priv = phydev->priv;
232 	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO,
240 	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd);
249 	ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
256 	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA);
263 static int gpy_config_init(struct phy_device *phydev)
268 	ret = phy_write(phydev, PHY_IMASK, 0);
273 	ret = phy_read(phydev, PHY_ISTAT);
277 static int gpy21x_config_init(struct phy_device *phydev)
279 	__set_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces);
280 	__set_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces);
282 	return gpy_config_init(phydev);
285 static int gpy_probe(struct phy_device *phydev)
287 	struct device *dev = &phydev->mdio.dev;
292 	if (!phydev->is_c45) {
293 		ret = phy_get_c45_ids(phydev);
301 	phydev->priv = priv;
305 		phydev->dev_flags |= PHY_F_NO_IRQ;
307 	fw_version = phy_read(phydev, PHY_FWV);
313 	ret = gpy_hwmon_register(phydev);
318 	phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n",
325 static bool gpy_sgmii_need_reaneg(struct phy_device *phydev)
327 	struct gpy_priv *priv = phydev->priv;
341 static bool gpy_2500basex_chk(struct phy_device *phydev)
345 	ret = phy_read(phydev, PHY_MIISTAT);
347 		phydev_err(phydev, "Error: MDIO register access failed: %d\n",
356 	phydev->speed = SPEED_2500;
357 	phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
358 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
363 static bool gpy_sgmii_aneg_en(struct phy_device *phydev)
367 	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL);
369 		phydev_err(phydev, "Error: MMD register access failed: %d\n",
377 static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl)
396 	ret =  phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB |
401 	return genphy_c45_restart_aneg(phydev);
404 static int gpy_config_aneg(struct phy_device *phydev)
410 	if (phydev->autoneg == AUTONEG_DISABLE) {
414 		return phydev->duplex != DUPLEX_FULL
415 			? genphy_setup_forced(phydev)
416 			: genphy_c45_pma_setup_forced(phydev);
419 	ret = gpy_config_mdix(phydev,  phydev->mdix_ctrl);
423 	ret = genphy_c45_an_config_aneg(phydev);
429 	adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
430 	ret = phy_modify_changed(phydev, MII_CTRL1000,
438 	ret = genphy_c45_check_and_restart_aneg(phydev, changed);
442 	if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
443 	    phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
449 	if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) ||
450 	    !gpy_sgmii_aneg_en(phydev))
474 	if (phydev->state != PHY_UP)
477 	ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS,
485 	return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
489 static int gpy_update_mdix(struct phy_device *phydev)
493 	ret = phy_read(phydev, PHY_CTL1);
498 		phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
501 			phydev->mdix_ctrl = ETH_TP_MDI_X;
503 			phydev->mdix_ctrl = ETH_TP_MDI;
505 	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY);
510 		phydev->mdix = ETH_TP_MDI_X;
512 		phydev->mdix = ETH_TP_MDI;
517 static int gpy_update_interface(struct phy_device *phydev)
522 	if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
523 	    phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
529 	switch (phydev->speed) {
531 		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
532 		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
535 			phydev_err(phydev,
544 		phydev->interface = PHY_INTERFACE_MODE_SGMII;
545 		if (gpy_sgmii_aneg_en(phydev))
550 		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
554 			phydev_err(phydev,
562 	if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) {
563 		ret = genphy_read_master_slave(phydev);
568 	return gpy_update_mdix(phydev);
571 static int gpy_read_status(struct phy_device *phydev)
575 	ret = genphy_update_link(phydev);
579 	phydev->speed = SPEED_UNKNOWN;
580 	phydev->duplex = DUPLEX_UNKNOWN;
581 	phydev->pause = 0;
582 	phydev->asym_pause = 0;
584 	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
585 		ret = genphy_c45_read_lpa(phydev);
590 		ret = phy_read(phydev, MII_STAT1000);
593 		mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
594 	} else if (phydev->autoneg == AUTONEG_DISABLE) {
595 		linkmode_zero(phydev->lp_advertising);
598 	ret = phy_read(phydev, PHY_MIISTAT);
602 	phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0;
603 	phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF;
606 		phydev->speed = SPEED_10;
609 		phydev->speed = SPEED_100;
612 		phydev->speed = SPEED_1000;
615 		phydev->speed = SPEED_2500;
619 	if (phydev->link) {
620 		ret = gpy_update_interface(phydev);
628 static int gpy_config_intr(struct phy_device *phydev)
632 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
635 	return phy_write(phydev, PHY_IMASK, mask);
638 static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev)
642 	reg = phy_read(phydev, PHY_ISTAT);
644 		phy_error(phydev);
665 		reg = gpy_mbox_read(phydev, REG_GPIO0_OUT);
667 			phy_error(phydev);
672 	phy_trigger_machine(phydev);
677 static int gpy_set_wol(struct phy_device *phydev,
680 	struct net_device *attach_dev = phydev->attached_dev;
689 		ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
696 		ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
703 		ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
711 		ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL);
716 		ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
725 		ret = phy_read(phydev, PHY_ISTAT);
730 		ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
739 		ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
744 		ret = phy_read(phydev, PHY_ISTAT);
749 			phy_trigger_machine(phydev);
755 	return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
758 static void gpy_get_wol(struct phy_device *phydev,
766 	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL);
770 	ret = phy_read(phydev, PHY_IMASK);
775 static int gpy_loopback(struct phy_device *phydev, bool enable)
777 	struct gpy_priv *priv = phydev->priv;
791 	ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set);
807 static int gpy115_loopback(struct phy_device *phydev, bool enable)
809 	struct gpy_priv *priv = phydev->priv;
812 		return gpy_loopback(phydev, enable);
815 		return gpy_loopback(phydev, 0);
817 	return genphy_soft_reset(phydev);