phy/mscc/mscc_serdes.c

14 static int pll5g_detune(struct phy_device *phydev)
19 	rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2);
22 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
25 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
29 static int pll5g_tune(struct phy_device *phydev)
34 	rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2);
36 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
39 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
43 static int vsc85xx_sd6g_pll_cfg_wr(struct phy_device *phydev,
50 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
56 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
60 static int vsc85xx_sd6g_common_cfg_wr(struct phy_device *phydev,
77 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
85 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
89 static int vsc85xx_sd6g_des_cfg_wr(struct phy_device *phydev,
105 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
109 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
113 static int vsc85xx_sd6g_ib_cfg0_wr(struct phy_device *phydev,
130 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
134 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
138 static int vsc85xx_sd6g_ib_cfg1_wr(struct phy_device *phydev,
154 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
158 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
162 static int vsc85xx_sd6g_ib_cfg2_wr(struct phy_device *phydev,
176 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
180 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
184 static int vsc85xx_sd6g_ib_cfg3_wr(struct phy_device *phydev,
195 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
199 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
203 static int vsc85xx_sd6g_ib_cfg4_wr(struct phy_device *phydev,
214 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
218 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
222 static int vsc85xx_sd6g_misc_cfg_wr(struct phy_device *phydev,
227 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
231 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
235 static int vsc85xx_sd6g_gp_cfg_wr(struct phy_device *phydev, const u32 gp_cfg_val)
239 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
243 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
247 static int vsc85xx_sd6g_dft_cfg2_wr(struct phy_device *phydev,
262 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
266 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
270 static int vsc85xx_sd6g_dft_cfg0_wr(struct phy_device *phydev,
280 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
284 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
289 static int vsc85xx_pll5g_cfg0_wr(struct phy_device *phydev,
300 	ret = vsc85xx_csr_write(phydev, MACRO_CTRL,
303 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);
307 int vsc85xx_sd6g_config_v2(struct phy_device *phydev)
325 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
328 	ret = pll5g_detune(phydev);
333 	ret = vsc85xx_sd6g_pll_cfg_wr(phydev, 3, pll_fsm_ctrl_data, 0);
336 	ret = vsc85xx_sd6g_common_cfg_wr(phydev, 0, 0, 0, qrate, if_mode, 0);
339 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
342 	ret = vsc85xx_sd6g_des_cfg_wr(phydev, 6, 2, 5, des_bw_ana_val, 0);
348 	ret = vsc85xx_sd6g_ib_cfg0_wr(phydev, ib_rtrm_adj, ib_sig_det_clk_sel_mm, 0, 0);
351 	ret = vsc85xx_sd6g_ib_cfg1_wr(phydev, 8, ib_tsdet_mm, 15, 0, 1);
354 	ret = vsc85xx_sd6g_ib_cfg2_wr(phydev, 3, 13, 5);
357 	ret = vsc85xx_sd6g_ib_cfg3_wr(phydev,  0, 31, 1, 31);
360 	ret = vsc85xx_sd6g_ib_cfg4_wr(phydev, 63, 63, 2, 63);
363 	ret = vsc85xx_sd6g_common_cfg_wr(phydev, 1, 1, 0, qrate, if_mode, 0);
366 	ret = vsc85xx_sd6g_misc_cfg_wr(phydev, 1);
369 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
374 	ret = vsc85xx_sd6g_pll_cfg_wr(phydev, 3, pll_fsm_ctrl_data, 1);
377 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
384 		ret = phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
387 		val32 = vsc85xx_csr_read(phydev, MACRO_CTRL,
396 	ret = vsc85xx_sd6g_misc_cfg_wr(phydev, 0);
399 	ret = vsc85xx_sd6g_common_cfg_wr(phydev, 1, 1, 0, qrate, if_mode, 1);
402 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
407 	ret = vsc85xx_sd6g_gp_cfg_wr(phydev, 768);
410 	ret = vsc85xx_sd6g_dft_cfg2_wr(phydev, 0, 2, 0, 0, 0, 1);
413 	ret = vsc85xx_sd6g_dft_cfg0_wr(phydev, 0, 0, 1);
416 	ret = vsc85xx_sd6g_des_cfg_wr(phydev, 6, 2, 5, des_bw_ana_val, 2);
419 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
424 	ret = vsc85xx_sd6g_ib_cfg1_wr(phydev, 8, ib_tsdet_cal, 15, 1, 0);
427 	ret = vsc85xx_sd6g_ib_cfg0_wr(phydev, ib_rtrm_adj, ib_sig_det_clk_sel_cal, 0, 0);
430 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
435 	ret = vsc85xx_sd6g_ib_cfg0_wr(phydev, ib_rtrm_adj,
439 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
445 		ret = vsc85xx_sd6g_gp_cfg_wr(phydev, 769);
448 		ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
452 		ret = vsc85xx_sd6g_gp_cfg_wr(phydev, 768);
455 		ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
460 	ret = vsc85xx_sd6g_ib_cfg1_wr(phydev, 8, ib_tsdet_cal, 15, 1, 1);
463 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
466 	ret = vsc85xx_sd6g_ib_cfg1_wr(phydev, 8, ib_tsdet_cal, 15, 0, 1);
469 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
477 		ret = phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
480 		val32 = vsc85xx_csr_read(phydev, MACRO_CTRL,
489 	ret = vsc85xx_sd6g_ib_cfg0_wr(phydev, ib_rtrm_adj, ib_sig_det_clk_sel_mm, 0, 1);
492 	ret = vsc85xx_sd6g_ib_cfg1_wr(phydev, 8, ib_tsdet_mm, 15, 0, 1);
495 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
500 	ret = vsc85xx_sd6g_common_cfg_wr(phydev, 1, 1, 0, qrate, if_mode, 0);
503 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
508 	ret = vsc85xx_sd6g_dft_cfg2_wr(phydev, 0, 0, 0, 0, 0, 0);
511 	ret = vsc85xx_sd6g_dft_cfg0_wr(phydev, 0, 0, 0);
514 	ret = vsc85xx_sd6g_des_cfg_wr(phydev, 6, 2, 5, des_bw_ana_val, 0);
517 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
522 	ret = pll5g_tune(phydev);
528 	ret = vsc85xx_sd6g_pll_cfg_wr(phydev, 3, pll_fsm_ctrl_data, 0);
531 	ret = vsc85xx_sd6g_common_cfg_wr(phydev, 0, 1, 0, qrate, if_mode, 0);
534 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
539 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_GPIO);
540 	ret = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
550 		ret = vsc8584_cmd(phydev, val);
552 			dev_err(&phydev->mdio.dev, "%s: QSGMII error: %d\n",
557 		phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
568 		ret = vsc8584_cmd(phydev, val);
570 			dev_err(&phydev->mdio.dev, "%s: SGMII error: %d\n",
575 		phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
577 		dev_err(&phydev->mdio.dev, "%s: invalid mac_if: %x\n",
581 	ret = phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
584 	ret = phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
587 	ret = vsc85xx_pll5g_cfg0_wr(phydev, 4);
590 	ret = phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
593 	ret = vsc85xx_sd6g_des_cfg_wr(phydev, 6, 2, 5, des_bw_ana_val, 0);
596 	ret = vsc85xx_sd6g_ib_cfg0_wr(phydev, ib_rtrm_adj, ib_sig_det_clk_sel_mm, 0, 1);
599 	ret = vsc85xx_sd6g_ib_cfg1_wr(phydev, 8, ib_tsdet_mm, 15, 0, 1);
602 	ret = vsc85xx_sd6g_common_cfg_wr(phydev, 1, 1, 0, qrate, if_mode, 0);
605 	ret = vsc85xx_sd6g_ib_cfg2_wr(phydev, 3, 13, 5);
608 	ret = vsc85xx_sd6g_ib_cfg3_wr(phydev,  0, 31, 1, 31);
611 	ret = vsc85xx_sd6g_ib_cfg4_wr(phydev, 63, 63, 2, 63);
614 	ret = vsc85xx_sd6g_misc_cfg_wr(phydev, 1);
617 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
622 	ret = vsc85xx_sd6g_pll_cfg_wr(phydev, 3, pll_fsm_ctrl_data, 1);
625 	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
633 		ret = phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
636 		val32 = vsc85xx_csr_read(phydev, MACRO_CTRL,
645 	ret = vsc85xx_sd6g_misc_cfg_wr(phydev, 0);
649 	return phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);