Lines Matching defs:phydev
113 static int vsc85xx_phy_read_page(struct phy_device *phydev)
115 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS);
118 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page)
120 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
123 static int vsc85xx_get_sset_count(struct phy_device *phydev)
125 struct vsc8531_private *priv = phydev->priv;
133 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data)
135 struct vsc8531_private *priv = phydev->priv;
146 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i)
148 struct vsc8531_private *priv = phydev->priv;
151 val = phy_read_paged(phydev, priv->hw_stats[i].page,
162 static void vsc85xx_get_stats(struct phy_device *phydev,
165 struct vsc8531_private *priv = phydev->priv;
172 data[i] = vsc85xx_get_stat(phydev, i);
175 static int vsc85xx_led_cntl_set(struct phy_device *phydev,
182 mutex_lock(&phydev->lock);
183 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
186 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
187 mutex_unlock(&phydev->lock);
192 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
196 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
205 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
210 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
220 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
231 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
237 return genphy_restart_aneg(phydev);
240 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
244 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
258 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
264 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
271 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
276 static int vsc85xx_wol_set(struct phy_device *phydev,
279 const u8 *mac_addr = phydev->attached_dev->dev_addr;
286 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
288 return phy_restore_page(phydev, rc, rc);
295 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
296 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
297 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
299 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
300 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
301 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
308 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
309 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
310 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
312 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
313 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
314 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
317 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
322 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
324 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
330 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
332 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
337 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
339 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
344 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
349 static void vsc85xx_wol_get(struct phy_device *phydev,
358 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
362 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
366 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
367 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
368 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
377 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
381 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
385 struct device *dev = &phydev->mdio.dev;
407 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
411 struct vsc8531_private *priv = phydev->priv;
412 struct device *dev = &phydev->mdio.dev;
423 phydev_err(phydev, "DT %s invalid\n", led);
431 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
436 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
444 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev,
447 struct vsc8531_private *priv = phydev->priv;
456 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop,
466 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
470 mutex_lock(&phydev->lock);
471 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
474 mutex_unlock(&phydev->lock);
479 static int vsc85xx_mac_if_set(struct phy_device *phydev,
485 mutex_lock(&phydev->lock);
486 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
506 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
510 rc = genphy_soft_reset(phydev);
513 mutex_unlock(&phydev->lock);
525 static int vsc85xx_update_rgmii_cntl(struct phy_device *phydev, u32 rgmii_cntl,
532 struct device *dev = &phydev->mdio.dev;
548 if (phy_interface_is_rgmii(phydev))
551 rx_delay = phy_get_internal_delay(phydev, dev, vsc85xx_internal_delay,
554 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
555 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
561 tx_delay = phy_get_internal_delay(phydev, dev, vsc85xx_internal_delay,
564 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
565 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
575 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
581 static int vsc85xx_default_config(struct phy_device *phydev)
583 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
585 return vsc85xx_update_rgmii_cntl(phydev, VSC8502_RGMII_CNTL,
590 static int vsc85xx_get_tunable(struct phy_device *phydev,
595 return vsc85xx_downshift_get(phydev, (u8 *)data);
601 static int vsc85xx_set_tunable(struct phy_device *phydev,
607 return vsc85xx_downshift_set(phydev, *(u8 *)data);
614 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val)
616 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
617 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
618 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
621 static int vsc8531_pre_init_seq_set(struct phy_device *phydev)
633 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD,
638 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
642 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
646 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
651 mutex_lock(&phydev->lock);
652 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
657 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val);
660 oldpage = phy_restore_page(phydev, oldpage, oldpage);
661 mutex_unlock(&phydev->lock);
666 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev)
691 mutex_lock(&phydev->lock);
692 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
697 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
700 oldpage = phy_restore_page(phydev, oldpage, oldpage);
701 mutex_unlock(&phydev->lock);
706 /* phydev->bus->mdio_lock should be locked when using this function */
707 int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)
709 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
710 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
714 return __phy_package_write(phydev, VSC88XX_BASE_ADDR, regnum, val);
717 /* phydev->bus->mdio_lock should be locked when using this function */
718 int phy_base_read(struct phy_device *phydev, u32 regnum)
720 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
721 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
725 return __phy_package_read(phydev, VSC88XX_BASE_ADDR, regnum);
728 u32 vsc85xx_csr_read(struct phy_device *phydev,
734 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
744 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
754 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
763 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
771 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);
774 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);
776 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
782 int vsc85xx_csr_write(struct phy_device *phydev,
787 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
797 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
801 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);
804 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));
813 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
822 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
829 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
836 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val)
838 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
839 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
840 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
844 int vsc8584_cmd(struct phy_device *phydev, u16 val)
849 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
852 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);
856 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);
861 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
873 static int vsc8584_micro_deassert_reset(struct phy_device *phydev,
878 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
890 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
896 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);
898 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);
900 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
906 static int vsc8584_micro_assert_reset(struct phy_device *phydev)
911 ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
915 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
918 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
920 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
922 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);
923 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);
925 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
927 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
929 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);
931 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
933 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
935 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |
939 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
941 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
943 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
949 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size,
954 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
956 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);
957 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);
960 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16);
964 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
966 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);
969 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
975 static int vsc8584_patch_fw(struct phy_device *phydev,
980 ret = vsc8584_micro_assert_reset(phydev);
982 dev_err(&phydev->mdio.dev,
987 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
993 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |
996 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |
998 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);
1001 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |
1005 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
1007 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1013 static bool vsc8574_is_serdes_init(struct phy_device *phydev)
1018 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1021 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
1027 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
1033 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1039 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1048 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1054 static int vsc8574_config_pre_init(struct phy_device *phydev)
1120 struct device *dev = &phydev->mdio.dev;
1127 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1130 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1132 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1134 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1141 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);
1143 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1145 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);
1146 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);
1147 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);
1148 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
1150 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1152 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1154 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1157 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1159 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1161 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1163 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1166 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1168 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1170 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1172 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1174 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1177 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1179 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1189 ret = vsc8584_get_fw_crc(phydev,
1196 serdes_init = vsc8574_is_serdes_init(phydev);
1199 ret = vsc8584_micro_assert_reset(phydev);
1212 if (vsc8584_patch_fw(phydev, fw))
1218 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1221 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);
1222 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);
1223 phy_base_write(phydev, MSCC_INT_MEM_CNTL,
1226 vsc8584_micro_deassert_reset(phydev, false);
1231 ret = vsc8584_get_fw_crc(phydev,
1242 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1245 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT |
1249 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1257 static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev,
1262 rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2);
1265 vsc85xx_csr_write(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2, rd_dat);
1269 static int vsc8584_mcb_rd_trig(struct phy_device *phydev,
1275 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr,
1281 phydev, MACRO_CTRL, mcb_reg_addr);
1285 static int vsc8584_mcb_wr_trig(struct phy_device *phydev,
1292 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr,
1298 phydev, MACRO_CTRL, mcb_reg_addr);
1302 static int vsc8584_pll5g_reset(struct phy_device *phydev)
1307 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0);
1313 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm);
1316 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0);
1324 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0);
1330 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm);
1333 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0);
1343 static int vsc8584_config_pre_init(struct phy_device *phydev)
1375 struct device *dev = &phydev->mdio.dev;
1380 ret = vsc8584_pll5g_reset(phydev);
1386 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1389 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1391 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1393 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1395 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
1397 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
1404 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);
1406 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);
1408 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1410 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
1412 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1414 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1416 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1418 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));
1420 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1423 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
1425 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));
1428 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1430 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1432 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1434 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1437 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1439 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1441 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1443 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1445 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1448 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1450 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1460 ret = vsc8584_get_fw_crc(phydev,
1468 if (vsc8584_patch_fw(phydev, fw))
1473 vsc8584_micro_deassert_reset(phydev, false);
1476 ret = vsc8584_get_fw_crc(phydev,
1486 ret = vsc8584_micro_assert_reset(phydev);
1491 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_GPIO);
1493 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg);
1498 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg);
1502 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1504 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1508 vsc8584_micro_deassert_reset(phydev, true);
1511 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1518 static void vsc8584_get_base_addr(struct phy_device *phydev)
1520 struct vsc8531_private *vsc8531 = phydev->priv;
1523 phy_lock_mdio_bus(phydev);
1524 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1526 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4);
1529 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
1531 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1532 phy_unlock_mdio_bus(phydev);
1538 vsc8531->ts_base_addr = phydev->mdio.addr;
1542 vsc8531->base_addr = phydev->mdio.addr + addr;
1548 vsc8531->base_addr = phydev->mdio.addr - addr;
1558 static void vsc85xx_coma_mode_release(struct phy_device *phydev)
1567 vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_EXTENDED_GPIO);
1568 __phy_modify(phydev, MSCC_PHY_GPIO_CONTROL_2,
1570 vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_STANDARD);
1573 static int vsc8584_config_host_serdes(struct phy_device *phydev)
1575 struct vsc8531_private *vsc8531 = phydev->priv;
1579 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1584 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1586 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
1588 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1595 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1599 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1606 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1611 ret = vsc8584_cmd(phydev, val);
1618 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1627 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1635 return vsc85xx_sd6g_config_v2(phydev);
1638 static int vsc8574_config_host_serdes(struct phy_device *phydev)
1640 struct vsc8531_private *vsc8531 = phydev->priv;
1644 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1649 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1651 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
1653 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1655 } else if (phy_interface_is_rgmii(phydev)) {
1662 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1666 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1671 if (!phy_interface_is_rgmii(phydev)) {
1674 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1679 ret = vsc8584_cmd(phydev, val);
1687 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1696 return vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1703 static int vsc8584_config_init(struct phy_device *phydev)
1705 struct vsc8531_private *vsc8531 = phydev->priv;
1709 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1711 phy_lock_mdio_bus(phydev);
1726 if (phy_package_init_once(phydev)) {
1731 WARN_ON(phydev->drv->phy_id_mask & 0xf);
1733 switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1738 ret = vsc8574_config_pre_init(phydev);
1741 ret = vsc8574_config_host_serdes(phydev);
1749 ret = vsc8584_config_pre_init(phydev);
1752 ret = vsc8584_config_host_serdes(phydev);
1755 vsc85xx_coma_mode_release(phydev);
1766 phy_unlock_mdio_bus(phydev);
1768 ret = vsc8584_macsec_init(phydev);
1772 ret = vsc8584_ptp_init(phydev);
1776 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
1780 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val);
1784 ret = vsc85xx_update_rgmii_cntl(phydev, VSC8572_RGMII_CNTL,
1790 ret = genphy_soft_reset(phydev);
1795 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1803 phy_unlock_mdio_bus(phydev);
1807 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev)
1812 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1819 ret = vsc8584_handle_ts_interrupt(phydev);
1824 vsc8584_handle_macsec_interrupt(phydev);
1827 phy_trigger_machine(phydev);
1832 static int vsc85xx_config_init(struct phy_device *phydev)
1835 struct vsc8531_private *vsc8531 = phydev->priv;
1837 rc = vsc85xx_default_config(phydev);
1841 rc = vsc85xx_mac_if_set(phydev, phydev->interface);
1845 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
1849 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask;
1852 rc = vsc8531_pre_init_seq_set(phydev);
1857 rc = vsc85xx_eee_init_seq_set(phydev);
1862 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1870 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb,
1877 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg,
1885 val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg);
1899 int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1901 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ);
1905 int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1907 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE);
1910 static int vsc8514_config_host_serdes(struct phy_device *phydev)
1915 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1920 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1923 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1927 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1932 ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
1936 ret = vsc8584_cmd(phydev,
1941 dev_err(&phydev->mdio.dev, "%s: QSGMII error: %d\n",
1953 vsc8584_micro_assert_reset(phydev);
1954 val = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1957 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, val);
1959 vsc8584_micro_deassert_reset(phydev, false);
1961 return vsc85xx_sd6g_config_v2(phydev);
1964 static int vsc8514_config_pre_init(struct phy_device *phydev)
1992 struct device *dev = &phydev->mdio.dev;
1997 ret = vsc8584_pll5g_reset(phydev);
2003 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
2006 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
2008 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
2010 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
2012 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
2014 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
2016 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
2019 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
2021 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
2023 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
2025 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
2027 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
2029 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
2031 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
2039 vsc8584_micro_deassert_reset(phydev, false);
2041 vsc8584_micro_assert_reset(phydev);
2042 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
2046 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg);
2051 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg);
2054 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
2056 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
2063 vsc8584_micro_deassert_reset(phydev, false);
2067 vsc8584_micro_deassert_reset(phydev, false);
2071 static int vsc8514_config_init(struct phy_device *phydev)
2073 struct vsc8531_private *vsc8531 = phydev->priv;
2076 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
2078 phy_lock_mdio_bus(phydev);
2091 if (phy_package_init_once(phydev)) {
2092 ret = vsc8514_config_pre_init(phydev);
2095 ret = vsc8514_config_host_serdes(phydev);
2098 vsc85xx_coma_mode_release(phydev);
2101 phy_unlock_mdio_bus(phydev);
2103 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK,
2109 ret = genphy_soft_reset(phydev);
2115 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
2123 phy_unlock_mdio_bus(phydev);
2127 static int vsc85xx_ack_interrupt(struct phy_device *phydev)
2131 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
2132 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2137 static int vsc85xx_config_intr(struct phy_device *phydev)
2141 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2142 rc = vsc85xx_ack_interrupt(phydev);
2146 vsc8584_config_macsec_intr(phydev);
2147 vsc8584_config_ts_intr(phydev);
2149 rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
2152 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
2155 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2159 rc = vsc85xx_ack_interrupt(phydev);
2165 static irqreturn_t vsc85xx_handle_interrupt(struct phy_device *phydev)
2169 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2171 phy_error(phydev);
2178 phy_trigger_machine(phydev);
2183 static int vsc85xx_config_aneg(struct phy_device *phydev)
2187 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
2191 return genphy_config_aneg(phydev);
2194 static int vsc85xx_read_status(struct phy_device *phydev)
2198 rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
2202 return genphy_read_status(phydev);
2205 static int vsc8514_probe(struct phy_device *phydev)
2212 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2216 phydev->priv = vsc8531;
2218 vsc8584_get_base_addr(phydev);
2219 devm_phy_package_join(&phydev->mdio.dev, phydev,
2226 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2231 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2234 static int vsc8574_probe(struct phy_device *phydev)
2241 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2245 phydev->priv = vsc8531;
2247 vsc8584_get_base_addr(phydev);
2248 devm_phy_package_join(&phydev->mdio.dev, phydev,
2255 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2260 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2263 static int vsc8584_probe(struct phy_device *phydev)
2271 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
2272 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n");
2276 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2280 phydev->priv = vsc8531;
2282 vsc8584_get_base_addr(phydev);
2283 devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr,
2290 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2295 if (phy_package_probe_once(phydev)) {
2296 ret = vsc8584_ptp_probe_once(phydev);
2301 ret = vsc8584_ptp_probe(phydev);
2305 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2308 static int vsc85xx_probe(struct phy_device *phydev)
2315 rate_magic = vsc85xx_edge_rate_magic_get(phydev);
2319 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2323 phydev->priv = vsc8531;
2330 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2335 return vsc85xx_dt_led_modes_get(phydev, default_mode);