Lines Matching defs:phy_base_read
718 int phy_base_read(struct phy_device *phydev, u32 regnum)
763 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
771 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);
774 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);
822 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
856 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);
918 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
925 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
931 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
939 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
966 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);
1021 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
1027 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
1033 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1039 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1130 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1150 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1170 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1177 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1389 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1395 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
1412 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1420 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1441 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1448 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1502 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1584 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1649 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1920 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1954 val = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
2006 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
2012 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
2023 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
2029 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
2054 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);