phy/mscc/mscc_macsec.c

23 				   enum macsec_bank bank, u32 reg)
34 		    MSCC_PHY_MACSEC_20_TARGET(bank >> 2));
36 	if (bank >> 2 == 0x1)
38 		bank &= 0x3;
40 		bank = 0;
45 		    MSCC_PHY_MACSEC_19_TARGET(bank));
62 				     enum macsec_bank bank, u32 reg, u32 val)
72 		    MSCC_PHY_MACSEC_20_TARGET(bank >> 2));
74 	if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3))
75 		bank &= 0x3;
78 		bank = 0;
85 		    MSCC_PHY_MACSEC_19_TARGET(bank));
97 					  enum macsec_bank bank)
100 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_CP_TAG,
107 					       enum macsec_bank bank,
110 	u32 port = (bank == MACSEC_INGR) ?
117 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_NCP,
134 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_CP,
154 					    enum macsec_bank bank)
158 	if (bank != MACSEC_INGR)
162 	val = vsc8584_macsec_phy_read(phydev, bank,
166 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CC_CONTROL,
169 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CP_TAG,
176 				      enum macsec_bank bank)
181 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
186 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
189 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_STATUS_CONTEXT_CTRL,
190 				 bank == MACSEC_INGR ? 0xe5880214 : 0xe5880218);
191 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_MISC_CONTROL,
192 				 MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX(bank == MACSEC_INGR ? 57 : 40) |
193 				 MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE(bank == MACSEC_INGR ? 1 : 2));
196 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
198 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
201 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PP_CTRL,
204 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_BLOCK_CTX_UPDATE, 0x3);
206 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
208 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
211 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_NON_VLAN_MTU_CHECK,
216 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_VLAN_MTU_CHECK(i),
220 	if (bank == MACSEC_EGR) {
221 		val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_INTR_CTRL_STATUS);
223 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_INTR_CTRL_STATUS, val);
225 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_FC_CFG,
233 	vsc8584_macsec_classification(phydev, bank);
234 	vsc8584_macsec_flow_default_action(phydev, bank, false);
235 	vsc8584_macsec_integrity_checks(phydev, bank);
238 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
245 				    enum macsec_bank bank)
252 		vsc8584_macsec_phy_write(phydev, bank, 0x1c + i, 0);
254 	val = vsc8584_macsec_phy_read(phydev, bank,
259 	vsc8584_macsec_phy_write(phydev, bank,
262 	val = vsc8584_macsec_phy_read(phydev, bank,
265 	vsc8584_macsec_phy_write(phydev, bank,
268 	val = vsc8584_macsec_phy_read(phydev, bank,
270 	if (bank == HOST_MAC)
278 	vsc8584_macsec_phy_write(phydev, bank,
281 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_PKTINF_CFG,
287 				 (bank == HOST_MAC ?
292 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG);
294 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MODE_CFG, val);
296 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG);
299 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG, val);
301 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ADV_CHK_CFG,
307 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_LFS_CFG);
309 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_LFS_CFG, val);
311 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ENA_CFG,
374 	enum macsec_bank bank = flow->bank;
382 	if (bank == MACSEC_INGR && flow->assoc_num >= 0) {
387 	if (bank == MACSEC_INGR && flow->match.sci && flow->rx_sa->sc->sci) {
394 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_LO(idx),
396 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_HI(idx),
403 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MAC_SA_MATCH_HI(idx),
409 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MISC_MATCH(idx), match);
410 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MASK(idx), mask);
418 		action = (bank == MACSEC_INGR) ?
428 	if (bank == MACSEC_INGR) {
435 	} else if (bank == MACSEC_EGR) {
445 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
449 						    enum macsec_bank bank)
455 		if (pos->assoc_num == ctx->sa.assoc_num && pos->bank == bank)
464 	enum macsec_bank bank = flow->bank;
467 	if ((flow->bank == MACSEC_INGR && flow->rx_sa && !flow->rx_sa->active) ||
468 	    (flow->bank == MACSEC_EGR && flow->tx_sa && !flow->tx_sa->active))
472 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_SET1, BIT(idx));
475 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
477 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
483 	enum macsec_bank bank = flow->bank;
487 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_CLEAR1, BIT(idx));
490 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
492 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
497 	if (flow->bank == MACSEC_INGR)
524 	enum macsec_bank bank = flow->bank;
545 	control |= (bank == MACSEC_EGR) ?
555 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
559 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
564 		vsc8584_macsec_phy_write(phydev, bank,
570 		vsc8584_macsec_phy_write(phydev, bank,
575 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
576 				 bank == MACSEC_INGR ?
579 	if (bank == MACSEC_INGR)
581 		vsc8584_macsec_phy_write(phydev, bank,
586 	sci = (__force u64)(bank == MACSEC_INGR ? flow->rx_sa->sc->sci : priv->secy->sci);
587 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
589 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
593 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
601 						     enum macsec_bank bank)
603 	unsigned long *bitmap = bank == MACSEC_INGR ?
619 	flow->bank = bank;
630 	unsigned long *bitmap = flow->bank == MACSEC_INGR ?
820 		if (flow->bank == MACSEC_INGR && flow->rx_sa &&
989 		if (flow->bank != MACSEC_EGR || !flow->has_transformation)