phy/mscc/mscc_macsec.c

22 static u32 vsc8584_macsec_phy_read(struct phy_device *phydev,
29 	rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC);
33 	__phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20,
42 	__phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19,
49 		val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19);
52 	val_l = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_17);
53 	val_h = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_18);
56 	phy_restore_page(phydev, rc, rc);
61 static void vsc8584_macsec_phy_write(struct phy_device *phydev,
67 	rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC);
71 	__phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20,
80 	__phy_write(phydev, MSCC_EXT_PAGE_MACSEC_17, (u16)val);
81 	__phy_write(phydev, MSCC_EXT_PAGE_MACSEC_18, (u16)(val >> 16));
83 	__phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19,
89 		val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19);
93 	phy_restore_page(phydev, rc, rc);
96 static void vsc8584_macsec_classification(struct phy_device *phydev,
100 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_CP_TAG,
106 static void vsc8584_macsec_flow_default_action(struct phy_device *phydev,
117 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_NCP,
134 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_CP,
153 static void vsc8584_macsec_integrity_checks(struct phy_device *phydev,
162 	val = vsc8584_macsec_phy_read(phydev, bank,
166 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CC_CONTROL,
169 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CP_TAG,
175 static void vsc8584_macsec_block_init(struct phy_device *phydev,
181 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
186 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
189 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_STATUS_CONTEXT_CTRL,
191 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_MISC_CONTROL,
196 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
198 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
201 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PP_CTRL,
204 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_BLOCK_CTX_UPDATE, 0x3);
206 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
208 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
211 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_NON_VLAN_MTU_CHECK,
216 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_VLAN_MTU_CHECK(i),
221 		val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_INTR_CTRL_STATUS);
223 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_INTR_CTRL_STATUS, val);
225 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_FC_CFG,
233 	vsc8584_macsec_classification(phydev, bank);
234 	vsc8584_macsec_flow_default_action(phydev, bank, false);
235 	vsc8584_macsec_integrity_checks(phydev, bank);
238 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
244 static void vsc8584_macsec_mac_init(struct phy_device *phydev,
252 		vsc8584_macsec_phy_write(phydev, bank, 0x1c + i, 0);
254 	val = vsc8584_macsec_phy_read(phydev, bank,
259 	vsc8584_macsec_phy_write(phydev, bank,
262 	val = vsc8584_macsec_phy_read(phydev, bank,
265 	vsc8584_macsec_phy_write(phydev, bank,
268 	val = vsc8584_macsec_phy_read(phydev, bank,
278 	vsc8584_macsec_phy_write(phydev, bank,
281 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_PKTINF_CFG,
292 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG);
294 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MODE_CFG, val);
296 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG);
299 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG, val);
301 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ADV_CHK_CFG,
307 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_LFS_CFG);
309 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_LFS_CFG, val);
311 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ENA_CFG,
319 static int __vsc8584_macsec_init(struct phy_device *phydev)
321 	struct vsc8531_private *priv = phydev->priv;
325 	vsc8584_macsec_block_init(phydev, MACSEC_INGR);
326 	vsc8584_macsec_block_init(phydev, MACSEC_EGR);
327 	vsc8584_macsec_mac_init(phydev, HOST_MAC);
328 	vsc8584_macsec_mac_init(phydev, LINE_MAC);
330 	vsc8584_macsec_phy_write(phydev, FC_BUFFER,
335 	val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG);
339 	vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG, val);
341 	vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG,
345 	val = vsc8584_macsec_phy_read(phydev, FC_BUFFER,
351 	vsc8584_macsec_phy_write(phydev, FC_BUFFER,
354 	val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG);
356 	vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val);
360 	val = vsc8584_macsec_phy_read(phydev, proc_bank,
364 	vsc8584_macsec_phy_write(phydev, proc_bank,
370 static void vsc8584_macsec_flow(struct phy_device *phydev,
373 	struct vsc8531_private *priv = phydev->priv;
394 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_LO(idx),
396 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_HI(idx),
403 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MAC_SA_MATCH_HI(idx),
409 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MISC_MATCH(idx), match);
410 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MASK(idx), mask);
445 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
451 	struct vsc8531_private *priv = ctx->phydev->priv;
461 static void vsc8584_macsec_flow_enable(struct phy_device *phydev,
472 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_SET1, BIT(idx));
475 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
477 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
480 static void vsc8584_macsec_flow_disable(struct phy_device *phydev,
487 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_CLEAR1, BIT(idx));
490 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
492 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
519 static int vsc8584_macsec_transformation(struct phy_device *phydev,
523 	struct vsc8531_private *priv = phydev->priv;
555 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
559 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
564 		vsc8584_macsec_phy_write(phydev, bank,
570 		vsc8584_macsec_phy_write(phydev, bank,
575 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
581 		vsc8584_macsec_phy_write(phydev, bank,
587 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
589 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
593 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
638 static void vsc8584_macsec_add_flow(struct phy_device *phydev,
642 	vsc8584_macsec_flow(phydev, flow);
645 static int vsc8584_macsec_default_flows(struct phy_device *phydev)
650 	flow = vsc8584_macsec_alloc_flow(phydev->priv, MACSEC_INGR);
662 	vsc8584_macsec_flow(phydev, flow);
663 	vsc8584_macsec_flow_enable(phydev, flow);
666 	flow = vsc8584_macsec_alloc_flow(phydev->priv, MACSEC_EGR);
677 	vsc8584_macsec_flow(phydev, flow);
678 	vsc8584_macsec_flow_enable(phydev, flow);
683 static void vsc8584_macsec_del_flow(struct phy_device *phydev,
686 	vsc8584_macsec_flow_disable(phydev, flow);
687 	vsc8584_macsec_free_flow(phydev->priv, flow);
693 	struct phy_device *phydev = ctx->phydev;
694 	struct vsc8531_private *priv = phydev->priv;
707 	vsc8584_macsec_add_flow(phydev, flow);
712 	ret = vsc8584_macsec_transformation(phydev, flow, ctx->sa.key);
714 		vsc8584_macsec_free_flow(phydev->priv, flow);
730 	vsc8584_macsec_add_flow(ctx->phydev, flow);
735 	ret = vsc8584_macsec_transformation(ctx->phydev, flow, ctx->sa.key);
737 		vsc8584_macsec_free_flow(ctx->phydev->priv, flow);
744 	struct vsc8531_private *priv = ctx->phydev->priv;
748 		vsc8584_macsec_flow_enable(ctx->phydev, flow);
755 	struct vsc8531_private *priv = ctx->phydev->priv;
759 		vsc8584_macsec_flow_disable(ctx->phydev, flow);
766 	struct vsc8531_private *priv = ctx->phydev->priv;
774 	vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_EGR,
776 	vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_INGR,
779 	return vsc8584_macsec_default_flows(ctx->phydev);
784 	struct vsc8531_private *priv = ctx->phydev->priv;
788 		vsc8584_macsec_del_flow(ctx->phydev, flow);
790 	vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_EGR, false);
791 	vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_INGR, false);
816 	struct vsc8531_private *priv = ctx->phydev->priv;
822 			vsc8584_macsec_del_flow(ctx->phydev, flow);
830 	struct phy_device *phydev = ctx->phydev;
831 	struct vsc8531_private *priv = phydev->priv;
843 	vsc8584_macsec_flow_enable(phydev, flow);
860 	vsc8584_macsec_flow_disable(ctx->phydev, flow);
866 	vsc8584_macsec_flow_enable(ctx->phydev, flow);
878 	vsc8584_macsec_del_flow(ctx->phydev, flow);
884 	struct phy_device *phydev = ctx->phydev;
885 	struct vsc8531_private *priv = phydev->priv;
897 	vsc8584_macsec_flow_enable(phydev, flow);
914 	vsc8584_macsec_flow_disable(ctx->phydev, flow);
920 	vsc8584_macsec_flow_enable(ctx->phydev, flow);
932 	vsc8584_macsec_del_flow(ctx->phydev, flow);
953 int vsc8584_macsec_init(struct phy_device *phydev)
955 	struct vsc8531_private *vsc8531 = phydev->priv;
957 	switch (phydev->phy_id & phydev->drv->phy_id_mask) {
964 		phydev->macsec_ops = &vsc8584_macsec_ops;
966 		return __vsc8584_macsec_init(phydev);
972 void vsc8584_handle_macsec_interrupt(struct phy_device *phydev)
974 	struct vsc8531_private *priv = phydev->priv;
979 	cause = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,
992 		val = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,
995 			vsc8584_macsec_flow_disable(phydev, flow);
1002 void vsc8584_config_macsec_intr(struct phy_device *phydev)
1004 	phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1005 	phy_write(phydev, MSCC_PHY_EXTENDED_INT, MSCC_PHY_EXTENDED_INT_MS_EGR);
1006 	phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1008 	vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_AIC_CTRL, 0xf);
1009 	vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_INTR_CTRL_STATUS,