net/phy/microchip.c

24 static int lan88xx_read_page(struct phy_device *phydev)
26 	return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS);
29 static int lan88xx_write_page(struct phy_device *phydev, int page)
31 	return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page);
34 static int lan88xx_phy_config_intr(struct phy_device *phydev)
38 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
40 		rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF);
41 		rc = phy_read(phydev, LAN88XX_INT_STS);
42 		rc = phy_write(phydev, LAN88XX_INT_MASK,
46 		rc = phy_write(phydev, LAN88XX_INT_MASK, 0);
51 		rc = phy_read(phydev, LAN88XX_INT_STS);
57 static irqreturn_t lan88xx_handle_interrupt(struct phy_device *phydev)
61 	irq_status = phy_read(phydev, LAN88XX_INT_STS);
63 		phy_error(phydev);
70 	phy_trigger_machine(phydev);
75 static int lan88xx_suspend(struct phy_device *phydev)
77 	struct lan88xx_priv *priv = phydev->priv;
81 		genphy_suspend(phydev);
86 static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
93 	save_page = phy_save_page(phydev);
95 		phydev_warn(phydev, "Failed to get current page\n");
100 	lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR);
102 	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
105 		phydev_warn(phydev, "Failed to write TR low data\n");
109 	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
112 		phydev_warn(phydev, "Failed to write TR high data\n");
120 	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
122 		phydev_warn(phydev, "Failed to write data in reg\n");
127 	val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
129 		phydev_warn(phydev, "TR Register[0x%X] configuration failed\n",
132 	return phy_restore_page(phydev, save_page, ret);
135 static void lan88xx_config_TR_regs(struct phy_device *phydev)
143 	err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
145 		phydev_warn(phydev, "Failed to Set Register[0x0F82]\n");
151 	err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
153 		phydev_warn(phydev, "Failed to Set Register[0x168C]\n");
159 	err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
161 		phydev_warn(phydev, "Failed to Set Register[0x17A2]\n");
168 	err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
170 		phydev_warn(phydev, "Failed to Set Register[0x16A0]\n");
176 	err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
178 		phydev_warn(phydev, "Failed to Set Register[0x16A6]\n");
184 	err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
186 		phydev_warn(phydev, "Failed to Set Register[0x16A4]\n");
192 	err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
194 		phydev_warn(phydev, "Failed to Set Register[0x16A8]\n");
201 	err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
203 		phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n");
210 	err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
212 		phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n");
219 	err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
221 		phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n");
226 	err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
228 		phydev_warn(phydev, "Failed to Set Register[0x1686]\n");
231 static int lan88xx_probe(struct phy_device *phydev)
233 	struct device *dev = &phydev->mdio.dev;
260 		(void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg);
266 	priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
267 	priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
269 	phydev->priv = priv;
274 static void lan88xx_remove(struct phy_device *phydev)
276 	struct device *dev = &phydev->mdio.dev;
277 	struct lan88xx_priv *priv = phydev->priv;
283 static int lan88xx_set_wol(struct phy_device *phydev,
286 	struct lan88xx_priv *priv = phydev->priv;
293 static void lan88xx_set_mdix(struct phy_device *phydev)
298 	switch (phydev->mdix_ctrl) {
312 	phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
313 	buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
316 	phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf);
317 	phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
320 static int lan88xx_config_init(struct phy_device *phydev)
325 	val = phy_read_mmd(phydev, MDIO_MMD_PCS,
329 	phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
333 	lan88xx_config_TR_regs(phydev);
338 static int lan88xx_config_aneg(struct phy_device *phydev)
340 	lan88xx_set_mdix(phydev);
342 	return genphy_config_aneg(phydev);
345 static void lan88xx_link_change_notify(struct phy_device *phydev)
354 	if (!phydev->autoneg && phydev->speed == 100) {
356 		temp = phy_read(phydev, LAN88XX_INT_MASK);
358 		phy_write(phydev, LAN88XX_INT_MASK, temp);
360 		temp = phy_read(phydev, MII_BMCR);
362 		phy_write(phydev, MII_BMCR, temp); /* set to 10 first */
364 		phy_write(phydev, MII_BMCR, temp); /* set to 100 later */
367 		temp = phy_read(phydev, LAN88XX_INT_STS);
370 		temp = phy_read(phydev, LAN88XX_INT_MASK);
372 		phy_write(phydev, LAN88XX_INT_MASK, temp);