Lines Matching defs:phydev
315 static int mtk_socphy_read_page(struct phy_device *phydev)
317 return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
320 static int mtk_socphy_write_page(struct phy_device *phydev, int page)
322 return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
331 static int cal_cycle(struct phy_device *phydev, int devad,
337 phy_modify_mmd(phydev, devad, regnum,
339 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
342 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
347 phydev_err(phydev, "Calibration cycle timeout\n");
351 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
353 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
355 phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
360 static int rext_fill_result(struct phy_device *phydev, u16 *buf)
362 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
364 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
370 static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
376 rext_fill_result(phydev, rext_cal_val);
381 static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
383 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
385 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
387 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
389 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
395 static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
404 tx_offset_fill_result(phydev, tx_offset_cal_val);
409 static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
421 switch (phydev->drv->phy_id) {
442 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
444 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
446 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
448 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
451 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
453 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
455 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
457 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
460 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
462 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
464 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
466 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
469 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
471 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
473 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
475 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
481 static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
489 tx_amp_fill_result(phydev, tx_amp_cal_val);
494 static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
500 if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
522 phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
527 static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
548 tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
553 static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
559 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
561 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
563 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
568 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
571 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
574 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
579 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
582 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
585 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
590 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
593 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
596 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
601 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
604 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
607 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
619 phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
622 ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
641 lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
651 upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
671 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
678 phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
682 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
689 phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
694 phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
701 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
703 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
705 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
707 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
714 static void mt798x_phy_common_finetune(struct phy_device *phydev)
716 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
718 __phy_write(phydev, 0x11, 0xc71);
719 __phy_write(phydev, 0x12, 0xc);
720 __phy_write(phydev, 0x10, 0x8fae);
723 __phy_write(phydev, 0x11, 0x2f00);
724 __phy_write(phydev, 0x12, 0xe);
725 __phy_write(phydev, 0x10, 0x8fb0);
728 __phy_write(phydev, 0x11, 0x55a0);
729 __phy_write(phydev, 0x12, 0x0);
730 __phy_write(phydev, 0x10, 0x83aa);
733 __phy_write(phydev, 0x11, 0x240);
734 __phy_write(phydev, 0x12, 0x0);
735 __phy_write(phydev, 0x10, 0x9680);
738 __phy_write(phydev, 0x11, 0x0);
739 __phy_write(phydev, 0x12, 0x0);
740 __phy_write(phydev, 0x10, 0x9686);
748 __phy_write(phydev, 0x11, 0xbaef);
749 __phy_write(phydev, 0x12, 0x2e);
750 __phy_write(phydev, 0x10, 0x968c);
751 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
754 static void mt7981_phy_finetune(struct phy_device *phydev)
769 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
772 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
774 __phy_write(phydev, 0x11, 0x600);
775 __phy_write(phydev, 0x12, 0x0);
776 __phy_write(phydev, 0x10, 0x8fc0);
779 __phy_write(phydev, 0x11, 0x4c2a);
780 __phy_write(phydev, 0x12, 0x3e);
781 __phy_write(phydev, 0x10, 0x8fa4);
786 __phy_write(phydev, 0x11, 0xd10a);
787 __phy_write(phydev, 0x12, 0x34);
788 __phy_write(phydev, 0x10, 0x8f82);
791 __phy_write(phydev, 0x11, 0x5555);
792 __phy_write(phydev, 0x12, 0x55);
793 __phy_write(phydev, 0x10, 0x8ec0);
794 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
797 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
802 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
805 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
806 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
807 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
808 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
809 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
810 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
811 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
812 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
813 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
814 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
817 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
819 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
823 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
824 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
826 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
829 static void mt7988_phy_finetune(struct phy_device *phydev)
838 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
841 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
843 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
845 __phy_write(phydev, 0x11, 0x500);
846 __phy_write(phydev, 0x12, 0x0);
847 __phy_write(phydev, 0x10, 0x8fc0);
854 __phy_write(phydev, 0x11, 0xb90a);
855 __phy_write(phydev, 0x12, 0x6f);
856 __phy_write(phydev, 0x10, 0x8f82);
859 __phy_write(phydev, 0x11, 0xfbba);
860 __phy_write(phydev, 0x12, 0xc3);
861 __phy_write(phydev, 0x10, 0x87f8);
863 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
866 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
871 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
874 static void mt798x_phy_eee(struct phy_device *phydev)
876 phy_modify_mmd(phydev, MDIO_MMD_VEND1,
883 phy_modify_mmd(phydev, MDIO_MMD_VEND1,
889 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
893 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
896 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
899 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
905 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
909 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
914 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
921 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
925 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
930 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
936 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
938 __phy_write(phydev, 0x11, 0xb);
939 __phy_write(phydev, 0x12, 0x0);
940 __phy_write(phydev, 0x10, 0x9690);
943 __phy_write(phydev, 0x11, 0x114f);
944 __phy_write(phydev, 0x12, 0x2);
945 __phy_write(phydev, 0x10, 0x969a);
948 __phy_write(phydev, 0x11, 0x3028);
949 __phy_write(phydev, 0x12, 0x0);
950 __phy_write(phydev, 0x10, 0x969e);
953 __phy_write(phydev, 0x11, 0x5010);
954 __phy_write(phydev, 0x12, 0x0);
955 __phy_write(phydev, 0x10, 0x96a0);
958 __phy_write(phydev, 0x11, 0x24a);
959 __phy_write(phydev, 0x12, 0x0);
960 __phy_write(phydev, 0x10, 0x96a8);
963 __phy_write(phydev, 0x11, 0x3210);
964 __phy_write(phydev, 0x12, 0x0);
965 __phy_write(phydev, 0x10, 0x96b8);
968 __phy_write(phydev, 0x11, 0x1463);
969 __phy_write(phydev, 0x12, 0x0);
970 __phy_write(phydev, 0x10, 0x96ca);
973 __phy_write(phydev, 0x11, 0x36);
974 __phy_write(phydev, 0x12, 0x0);
975 __phy_write(phydev, 0x10, 0x8f80);
976 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
978 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
979 __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
982 __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
984 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
986 phy_modify_mmd(phydev, MDIO_MMD_VEND1,
992 static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
1002 ret = tx_vcm_cal_sw(phydev, pair_n);
1013 static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
1023 ret = rext_cal_efuse(phydev, buf);
1026 ret = tx_offset_cal_efuse(phydev, buf);
1029 ret = tx_amp_cal_efuse(phydev, buf);
1032 ret = tx_r50_cal_efuse(phydev, buf, pair_n);
1044 static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
1052 ret = cal_efuse(phydev, cal_item, start_pair,
1056 ret = cal_sw(phydev, cal_item, start_pair, end_pair);
1063 phydev_err(phydev, "cal %d failed\n", cal_item);
1070 static int mt798x_phy_calibration(struct phy_device *phydev)
1077 cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
1090 phydev_err(phydev, "invalid efuse data\n");
1095 ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1098 ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1101 ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1104 ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
1107 ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
1116 static int mt798x_phy_config_init(struct phy_device *phydev)
1118 switch (phydev->drv->phy_id) {
1120 mt7981_phy_finetune(phydev);
1123 mt7988_phy_finetune(phydev);
1127 mt798x_phy_common_finetune(phydev);
1128 mt798x_phy_eee(phydev);
1130 return mt798x_phy_calibration(phydev);
1133 static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
1137 struct mtk_socphy_priv *priv = phydev->priv;
1148 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
1156 static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
1160 struct mtk_socphy_priv *priv = phydev->priv;
1171 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
1178 static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
1194 err = mt798x_phy_hw_led_blink_set(phydev, index, blinking);
1198 return mt798x_phy_hw_led_on_set(phydev, index, false);
1201 static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
1206 err = mt798x_phy_hw_led_blink_set(phydev, index, false);
1210 return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
1222 static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
1235 static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
1241 struct mtk_socphy_priv *priv = phydev->priv;
1247 on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1253 blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1306 static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
1310 struct mtk_socphy_priv *priv = phydev->priv;
1353 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
1364 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
1369 static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
1371 struct mtk_socphy_shared *priv = phydev->shared->priv;
1379 if (polarities & BIT(phydev->mdio.addr))
1385 static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev)
1392 phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
1395 mt7988_phy_led_get_polarity(phydev, index) ?
1399 pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
1401 dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n");
1406 static int mt7988_phy_probe_shared(struct phy_device *phydev)
1408 struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
1409 struct mtk_socphy_shared *shared = phydev->shared->priv;
1440 static void mt798x_phy_leds_state_init(struct phy_device *phydev)
1445 mt798x_phy_led_hw_control_get(phydev, i, NULL);
1448 static int mt7988_phy_probe(struct phy_device *phydev)
1454 if (phydev->mdio.addr > 3)
1457 err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
1462 if (phy_package_probe_once(phydev)) {
1463 err = mt7988_phy_probe_shared(phydev);
1468 shared = phydev->shared->priv;
1469 priv = &shared->priv[phydev->mdio.addr];
1471 phydev->priv = priv;
1473 mt798x_phy_leds_state_init(phydev);
1475 err = mt7988_phy_fix_leds_polarities(phydev);
1483 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
1486 return mt798x_phy_calibration(phydev);
1489 static int mt7981_phy_probe(struct phy_device *phydev)
1493 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv),
1498 phydev->priv = priv;
1500 mt798x_phy_leds_state_init(phydev);
1502 return mt798x_phy_calibration(phydev);