Lines Matching defs:phydev
32 static int dp83tg720_config_aneg(struct phy_device *phydev)
38 return genphy_c45_pma_baset1_setup_master_slave(phydev);
41 static int dp83tg720_read_status(struct phy_device *phydev)
46 phydev->pause = 0;
47 phydev->asym_pause = 0;
52 phy_sts = phy_read(phydev, DP83TG720S_MII_REG_10);
53 phydev->link = !!(phy_sts & DP83TG720S_LINK_STATUS);
54 if (!phydev->link) {
62 ret = phy_init_hw(phydev);
68 ret = dp83tg720_config_aneg(phydev);
72 phydev->speed = SPEED_UNKNOWN;
73 phydev->duplex = DUPLEX_UNKNOWN;
79 ret = genphy_c45_pma_baset1_read_master_slave(phydev);
83 phydev->duplex = DUPLEX_FULL;
84 phydev->speed = SPEED_1000;
90 static int dp83tg720_get_sqi(struct phy_device *phydev)
94 if (!phydev->link)
97 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_SQI_REG_1);
104 static int dp83tg720_get_sqi_max(struct phy_device *phydev)
109 static int dp83tg720_config_rgmii_delay(struct phy_device *phydev)
114 switch (phydev->interface) {
135 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
140 static int dp83tg720_config_init(struct phy_device *phydev)
147 ret = phy_write(phydev, DP83TG720S_PHY_RESET, DP83TG720S_HW_RESET);
157 if (phy_interface_is_rgmii(phydev))
158 return dp83tg720_config_rgmii_delay(phydev);