net/phy/dp83tc811.c

78 static int dp83811_ack_interrupt(struct phy_device *phydev)
82 	err = phy_read(phydev, MII_DP83811_INT_STAT1);
86 	err = phy_read(phydev, MII_DP83811_INT_STAT2);
90 	err = phy_read(phydev, MII_DP83811_INT_STAT3);
97 static int dp83811_set_wol(struct phy_device *phydev,
100 	struct net_device *ndev = phydev->attached_dev;
113 		phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA1,
115 		phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA2,
117 		phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA3,
120 		value = phy_read_mmd(phydev, DP83811_DEVADDR,
128 			phy_write_mmd(phydev, DP83811_DEVADDR,
131 			phy_write_mmd(phydev, DP83811_DEVADDR,
134 			phy_write_mmd(phydev, DP83811_DEVADDR,
143 		phy_read(phydev, MII_DP83811_INT_STAT1);
148 		return phy_write_mmd(phydev, DP83811_DEVADDR,
151 		return phy_clear_bits_mmd(phydev, DP83811_DEVADDR,
157 static void dp83811_get_wol(struct phy_device *phydev,
166 	value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
172 		sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
177 		sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
182 		sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
195 static int dp83811_config_intr(struct phy_device *phydev)
199 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
200 		err = dp83811_ack_interrupt(phydev);
204 		misr_status = phy_read(phydev, MII_DP83811_INT_STAT1);
217 		err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status);
221 		misr_status = phy_read(phydev, MII_DP83811_INT_STAT2);
232 		err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status);
236 		misr_status = phy_read(phydev, MII_DP83811_INT_STAT3);
244 		err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status);
247 		err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
251 		err = phy_write(phydev, MII_DP83811_INT_STAT2, 0);
255 		err = phy_write(phydev, MII_DP83811_INT_STAT3, 0);
259 		err = dp83811_ack_interrupt(phydev);
265 static irqreturn_t dp83811_handle_interrupt(struct phy_device *phydev)
277 	irq_status = phy_read(phydev, MII_DP83811_INT_STAT1);
279 		phy_error(phydev);
285 	irq_status = phy_read(phydev, MII_DP83811_INT_STAT2);
287 		phy_error(phydev);
293 	irq_status = phy_read(phydev, MII_DP83811_INT_STAT3);
295 		phy_error(phydev);
304 	phy_trigger_machine(phydev);
309 static int dp83811_config_aneg(struct phy_device *phydev)
313 	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
314 		value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
315 		if (phydev->autoneg == AUTONEG_ENABLE) {
316 			err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
321 			err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
328 	return genphy_config_aneg(phydev);
331 static int dp83811_config_init(struct phy_device *phydev)
335 	value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
336 	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
337 		err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
340 		err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
350 	return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
354 static int dp83811_phy_reset(struct phy_device *phydev)
358 	err = phy_write(phydev, MII_DP83811_RESET_CTRL, DP83811_HW_RESET);
365 static int dp83811_suspend(struct phy_device *phydev)
369 	value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
372 		genphy_suspend(phydev);
377 static int dp83811_resume(struct phy_device *phydev)
379 	genphy_resume(phydev);
381 	phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,