Lines Matching defs:phydev

21 int __bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val)
25 rc = __phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
29 return __phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
33 int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val)
37 phy_lock_mdio_bus(phydev);
38 rc = __bcm_phy_write_exp(phydev, reg, val);
39 phy_unlock_mdio_bus(phydev);
45 int __bcm_phy_read_exp(struct phy_device *phydev, u16 reg)
49 val = __phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
53 val = __phy_read(phydev, MII_BCM54XX_EXP_DATA);
56 __phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
62 int bcm_phy_read_exp(struct phy_device *phydev, u16 reg)
66 phy_lock_mdio_bus(phydev);
67 rc = __bcm_phy_read_exp(phydev, reg);
68 phy_unlock_mdio_bus(phydev);
74 int __bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set)
78 ret = __phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
82 ret = __phy_read(phydev, MII_BCM54XX_EXP_DATA);
90 return __phy_write(phydev, MII_BCM54XX_EXP_DATA, new);
94 int bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set)
98 phy_lock_mdio_bus(phydev);
99 ret = __bcm_phy_modify_exp(phydev, reg, mask, set);
100 phy_unlock_mdio_bus(phydev);
106 int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
111 phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK |
113 return phy_read(phydev, MII_BCM54XX_AUX_CTL);
117 int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
119 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
123 int bcm_phy_write_misc(struct phy_device *phydev,
129 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
134 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
136 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
141 rc = bcm_phy_write_exp(phydev, tmp, val);
147 int bcm_phy_read_misc(struct phy_device *phydev,
153 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
158 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
160 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
165 rc = bcm_phy_read_exp(phydev, tmp);
171 int bcm_phy_ack_intr(struct phy_device *phydev)
176 reg = phy_read(phydev, MII_BCM54XX_ISR);
184 int bcm_phy_config_intr(struct phy_device *phydev)
188 reg = phy_read(phydev, MII_BCM54XX_ECR);
192 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
193 err = bcm_phy_ack_intr(phydev);
198 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
201 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
205 err = bcm_phy_ack_intr(phydev);
211 irqreturn_t bcm_phy_handle_interrupt(struct phy_device *phydev)
215 irq_status = phy_read(phydev, MII_BCM54XX_ISR);
217 phy_error(phydev);
226 irq_mask = phy_read(phydev, MII_BCM54XX_IMR);
228 phy_error(phydev);
236 phy_trigger_machine(phydev);
242 int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow)
244 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
245 return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
249 int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow,
252 return phy_write(phydev, MII_BCM54XX_SHD,
259 int __bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb)
263 val = __phy_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
267 return __phy_read(phydev, MII_BCM54XX_RDB_DATA);
271 int bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb)
275 phy_lock_mdio_bus(phydev);
276 ret = __bcm_phy_read_rdb(phydev, rdb);
277 phy_unlock_mdio_bus(phydev);
283 int __bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val)
287 ret = __phy_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
291 return __phy_write(phydev, MII_BCM54XX_RDB_DATA, val);
295 int bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val)
299 phy_lock_mdio_bus(phydev);
300 ret = __bcm_phy_write_rdb(phydev, rdb, val);
301 phy_unlock_mdio_bus(phydev);
307 int __bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask, u16 set)
311 ret = __phy_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
315 ret = __phy_read(phydev, MII_BCM54XX_RDB_DATA);
323 return __phy_write(phydev, MII_BCM54XX_RDB_DATA, new);
327 int bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask, u16 set)
331 phy_lock_mdio_bus(phydev);
332 ret = __bcm_phy_modify_rdb(phydev, rdb, mask, set);
333 phy_unlock_mdio_bus(phydev);
339 int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down)
344 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
349 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
352 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
359 if (phydev->autoneg == AUTONEG_ENABLE)
368 return bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
372 int bcm_phy_set_eee(struct phy_device *phydev, bool enable)
377 val = phy_read_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL);
386 phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val);
389 val = phy_read_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV);
394 phydev->supported))
397 phydev->supported))
405 phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val);
411 int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count)
415 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
425 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
443 int bcm_phy_downshift_set(struct phy_device *phydev, u8 count)
454 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
463 return bcm54xx_auxctl_write(phydev,
468 ret = bcm54xx_auxctl_write(phydev,
475 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
493 return bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR2, val);
515 int bcm_phy_get_sset_count(struct phy_device *phydev)
521 void bcm_phy_get_strings(struct phy_device *phydev, u8 *data)
534 static u64 bcm_phy_get_stat(struct phy_device *phydev, u64 *shadow,
542 val = phy_read(phydev, stat.reg);
544 val = phy_read_mmd(phydev, stat.devad, stat.reg);
557 void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
563 data[i] = bcm_phy_get_stat(phydev, shadow, i);
567 void bcm_phy_r_rc_cal_reset(struct phy_device *phydev)
570 bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0010);
573 bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0000);
577 int bcm_phy_28nm_a0b0_afe_config_init(struct phy_device *phydev)
582 bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
585 bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
590 bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
593 bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
596 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);
598 bcm_phy_r_rc_cal_reset(phydev);
601 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
604 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
607 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
610 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
613 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
619 int bcm_phy_enable_jumbo(struct phy_device *phydev)
623 ret = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL);
628 ret = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
637 return phy_set_bits(phydev, MII_BCM54XX_ECR, MII_BCM54XX_ECR_FIFOE);
641 static int __bcm_phy_enable_rdb_access(struct phy_device *phydev)
643 return __bcm_phy_write_exp(phydev, BCM54XX_EXP_REG7E, 0);
646 static int __bcm_phy_enable_legacy_access(struct phy_device *phydev)
648 return __bcm_phy_write_rdb(phydev, BCM54XX_RDB_REG0087,
652 static int _bcm_phy_cable_test_start(struct phy_device *phydev, bool is_rdb)
660 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
661 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
662 phy_write(phydev, MII_CTRL1000, 0);
664 phy_lock_mdio_bus(phydev);
666 ret = __bcm_phy_enable_legacy_access(phydev);
676 ret = __bcm_phy_modify_exp(phydev, BCM54XX_EXP_ECD_CTRL, mask, set);
681 ret = __bcm_phy_enable_rdb_access(phydev) ? : ret;
683 phy_unlock_mdio_bus(phydev);
717 static int bcm_phy_report_length(struct phy_device *phydev, int pair)
721 val = __bcm_phy_read_exp(phydev,
729 ethnl_cable_test_fault_length(phydev, pair, val);
734 static int _bcm_phy_cable_test_get_status(struct phy_device *phydev,
741 phy_lock_mdio_bus(phydev);
744 ret = __bcm_phy_enable_legacy_access(phydev);
749 ret = __bcm_phy_read_exp(phydev, BCM54XX_EXP_ECD_CTRL);
758 ret = __bcm_phy_read_exp(phydev, BCM54XX_EXP_ECD_FAULT_TYPE);
767 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
769 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
771 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
773 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
777 bcm_phy_report_length(phydev, 0);
779 bcm_phy_report_length(phydev, 1);
781 bcm_phy_report_length(phydev, 2);
783 bcm_phy_report_length(phydev, 3);
790 ret = __bcm_phy_enable_rdb_access(phydev) ? : ret;
792 phy_unlock_mdio_bus(phydev);
797 int bcm_phy_cable_test_start(struct phy_device *phydev)
799 return _bcm_phy_cable_test_start(phydev, false);
803 int bcm_phy_cable_test_get_status(struct phy_device *phydev, bool *finished)
805 return _bcm_phy_cable_test_get_status(phydev, finished, false);
813 int bcm_phy_cable_test_start_rdb(struct phy_device *phydev)
815 return _bcm_phy_cable_test_start(phydev, true);
819 int bcm_phy_cable_test_get_status_rdb(struct phy_device *phydev,
822 return _bcm_phy_cable_test_get_status(phydev, finished, true);
832 int bcm_phy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
834 struct net_device *ndev = phydev->attached_dev;
852 ret = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS);
856 ret = bcm_phy_read_exp(phydev, BCM54XX_WOL_MAIN_CTL);
863 if (phy_interrupt_is_valid(phydev))
864 disable_irq_wake(phydev->irq);
867 ret = bcm_phy_write_exp(phydev, BCM54XX_WOL_INT_MASK,
875 return bcm_phy_write_exp(phydev, BCM54XX_WOL_MAIN_CTL, ctl);
919 ret = bcm_phy_write_exp(phydev,
927 ret = bcm_phy_write_exp(phydev, BCM54XX_WOL_MPD_DATA2(2 - i),
932 ret = bcm_phy_write_exp(phydev, BCM54XX_WOL_MASK(2 - i),
956 ret = bcm_phy_write_exp(phydev, BCM54XX_WOL_MAIN_CTL, ctl);
961 ret = bcm_phy_read_exp(phydev, BCM54XX_TOP_MISC_LED_CTL);
966 ret = bcm_phy_write_exp(phydev, BCM54XX_TOP_MISC_LED_CTL, ret);
971 ret = bcm_phy_write_exp(phydev, BCM54XX_WOL_INT_MASK, 0);
975 if (phy_interrupt_is_valid(phydev))
976 enable_irq_wake(phydev->irq);
982 void bcm_phy_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
984 struct net_device *ndev = phydev->attached_dev;
993 ret = bcm_phy_read_exp(phydev, BCM54XX_WOL_MAIN_CTL);
1003 ret = bcm_phy_read_exp(phydev,
1042 int bcm_phy_led_brightness_set(struct phy_device *phydev,
1056 ret = bcm_phy_read_shadow(phydev, reg);
1065 return bcm_phy_write_shadow(phydev, reg, ret);