net/phy/adin1100.c

76 static int adin_read_status(struct phy_device *phydev)
80 	ret = genphy_c45_read_status(phydev);
84 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, ADIN_AN_PHY_INST_STATUS);
89 		phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
92 		phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
97 static int adin_config_aneg(struct phy_device *phydev)
99 	struct adin_priv *priv = phydev->priv;
102 	if (phydev->autoneg == AUTONEG_DISABLE) {
103 		ret = genphy_c45_pma_setup_forced(phydev);
108 			ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
111 			ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
117 		return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
120 	ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
126 		ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
135 		ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
142 	return genphy_c45_config_aneg(phydev);
145 static int adin_phy_ack_intr(struct phy_device *phydev)
148 	int rc = phy_read_mmd(phydev, MDIO_MMD_VEND2,
154 static int adin_config_intr(struct phy_device *phydev)
159 	ret = adin_phy_ack_intr(phydev);
163 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
168 	return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
173 static irqreturn_t adin_phy_handle_interrupt(struct phy_device *phydev)
177 	irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND2,
180 		phy_error(phydev);
187 	phy_trigger_machine(phydev);
192 static int adin_set_powerdown_mode(struct phy_device *phydev, bool en)
198 	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
203 	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
208 static int adin_suspend(struct phy_device *phydev)
210 	return adin_set_powerdown_mode(phydev, true);
213 static int adin_resume(struct phy_device *phydev)
215 	return adin_set_powerdown_mode(phydev, false);
218 static int adin_set_loopback(struct phy_device *phydev, bool enable)
221 		return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
225 	return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
229 static int adin_soft_reset(struct phy_device *phydev)
233 	ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);
237 	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
242 static int adin_get_features(struct phy_device *phydev)
244 	struct adin_priv *priv = phydev->priv;
245 	struct device *dev = &phydev->mdio.dev;
249 	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);
256 	phydev_dbg(phydev, "PHY supports 2.4V TX level: %s\n",
267 			phydev_info(phydev,
272 			       phydev->supported);
274 	return genphy_c45_pma_read_abilities(phydev);
277 static int adin_get_sqi(struct phy_device *phydev)
283 	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);
289 	ret = phy_read_mmd(phydev, MDIO_STAT1, ADIN_MSE_VAL);
302 static int adin_get_sqi_max(struct phy_device *phydev)
307 static int adin_probe(struct phy_device *phydev)
309 	struct device *dev = &phydev->mdio.dev;
316 	phydev->priv = priv;