Lines Matching defs:phydev
249 static u32 adin_get_reg_value(struct phy_device *phydev,
254 struct device *dev = &phydev->mdio.dev;
263 phydev_warn(phydev,
272 static int adin_config_rgmii_mode(struct phy_device *phydev)
277 if (!phy_interface_is_rgmii(phydev))
278 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
282 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
288 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
289 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
292 val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",
301 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
302 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
305 val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",
314 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
318 static int adin_config_rmii_mode(struct phy_device *phydev)
323 if (phydev->interface != PHY_INTERFACE_MODE_RMII)
324 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
328 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
334 val = adin_get_reg_value(phydev, "adi,fifo-depth-bits",
341 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
345 static int adin_get_downshift(struct phy_device *phydev, u8 *data)
349 val = phy_read(phydev, ADIN1300_PHY_CTRL2);
353 cnt = phy_read(phydev, ADIN1300_PHY_CTRL3);
365 static int adin_set_downshift(struct phy_device *phydev, u8 cnt)
371 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2,
379 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3,
385 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2,
389 static int adin_get_edpd(struct phy_device *phydev, u16 *tx_interval)
393 val = phy_read(phydev, ADIN1300_PHY_CTRL_STATUS2);
410 static int adin_set_edpd(struct phy_device *phydev, u16 tx_interval)
415 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2,
432 return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2,
437 static int adin_get_fast_down(struct phy_device *phydev, u8 *msecs)
441 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_FLD_EN_REG);
453 static int adin_set_fast_down(struct phy_device *phydev, const u8 *msecs)
456 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
461 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
468 static int adin_get_tunable(struct phy_device *phydev,
473 return adin_get_downshift(phydev, data);
475 return adin_get_edpd(phydev, data);
477 return adin_get_fast_down(phydev, data);
483 static int adin_set_tunable(struct phy_device *phydev,
488 return adin_set_downshift(phydev, *(const u8 *)data);
490 return adin_set_edpd(phydev, *(const u16 *)data);
492 return adin_set_fast_down(phydev, data);
498 static int adin_config_clk_out(struct phy_device *phydev)
500 struct device *dev = &phydev->mdio.dev;
514 phydev_err(phydev, "invalid adi,phy-output-clock\n");
521 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG_REG,
525 static int adin_config_init(struct phy_device *phydev)
529 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
531 rc = adin_config_rgmii_mode(phydev);
535 rc = adin_config_rmii_mode(phydev);
539 rc = adin_set_downshift(phydev, 4);
543 rc = adin_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
547 rc = adin_config_clk_out(phydev);
551 phydev_dbg(phydev, "PHY is using mode '%s'\n",
552 phy_modes(phydev->interface));
557 static int adin_phy_ack_intr(struct phy_device *phydev)
560 int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG);
565 static int adin_phy_config_intr(struct phy_device *phydev)
569 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
570 err = adin_phy_ack_intr(phydev);
574 err = phy_set_bits(phydev, ADIN1300_INT_MASK_REG,
577 err = phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,
582 err = adin_phy_ack_intr(phydev);
588 static irqreturn_t adin_phy_handle_interrupt(struct phy_device *phydev)
592 irq_status = phy_read(phydev, ADIN1300_INT_STATUS_REG);
594 phy_error(phydev);
601 phy_trigger_machine(phydev);
606 static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad,
621 phydev_err(phydev,
628 static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum)
630 struct mii_bus *bus = phydev->mdio.bus;
631 int phy_addr = phydev->mdio.addr;
635 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
647 static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,
650 struct mii_bus *bus = phydev->mdio.bus;
651 int phy_addr = phydev->mdio.addr;
655 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
667 static int adin_config_mdix(struct phy_device *phydev)
674 switch (phydev->mdix_ctrl) {
687 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
701 return phy_write(phydev, ADIN1300_PHY_CTRL1, reg);
704 static int adin_config_aneg(struct phy_device *phydev)
708 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN);
712 ret = phy_set_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN);
716 ret = adin_config_mdix(phydev);
720 return genphy_config_aneg(phydev);
723 static int adin_mdix_update(struct phy_device *phydev)
729 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
739 phydev->mdix = ETH_TP_MDI_X;
741 phydev->mdix = ETH_TP_MDI;
750 reg = phy_read(phydev, ADIN1300_PHY_STATUS1);
757 phydev->mdix = ETH_TP_MDI_X;
759 phydev->mdix = ETH_TP_MDI;
764 static int adin_read_status(struct phy_device *phydev)
768 ret = adin_mdix_update(phydev);
772 return genphy_read_status(phydev);
775 static int adin_soft_reset(struct phy_device *phydev)
780 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
789 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
795 static int adin_get_sset_count(struct phy_device *phydev)
800 static void adin_get_strings(struct phy_device *phydev, u8 *data)
810 static int adin_read_mmd_stat_regs(struct phy_device *phydev,
816 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1);
825 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2);
835 static u64 adin_get_stat(struct phy_device *phydev, int i)
838 struct adin_priv *priv = phydev->priv;
843 ret = adin_read_mmd_stat_regs(phydev, stat, &val);
847 ret = phy_read(phydev, stat->reg1);
858 static void adin_get_stats(struct phy_device *phydev,
864 rc = phy_read(phydev, ADIN1300_RX_ERR_CNT);
869 data[i] = adin_get_stat(phydev, i);
872 static int adin_probe(struct phy_device *phydev)
874 struct device *dev = &phydev->mdio.dev;
881 phydev->priv = priv;
886 static int adin_cable_test_start(struct phy_device *phydev)
890 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN);
894 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN);
901 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN,
927 static int adin_cable_test_report_pair(struct phy_device *phydev,
933 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
940 ret = ethnl_cable_test_result(phydev, pair, fault_rslt);
944 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
953 return ethnl_cable_test_fault_length(phydev, pair, ret * 100);
959 static int adin_cable_test_report(struct phy_device *phydev)
965 ret = adin_cable_test_report_pair(phydev, pair);
973 static int adin_cable_test_get_status(struct phy_device *phydev,
980 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN);
989 return adin_cable_test_report(phydev);