Lines Matching defs:xpcs
10 #include <linux/pcs/pcs-xpcs.h>
14 #include "pcs-xpcs.h"
151 int (*pma_config)(struct dw_xpcs *xpcs);
176 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface)
180 compat = xpcs_find_compat(xpcs->id, interface);
203 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg)
205 return mdiodev_c45_read(xpcs->mdiodev, dev, reg);
208 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)
210 return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val);
213 static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg,
216 return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set);
219 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)
221 return xpcs_read(xpcs, dev, DW_VENDOR | reg);
224 static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg,
227 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val);
230 int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg)
232 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg);
235 int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val)
237 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val);
240 static int xpcs_dev_flag(struct dw_xpcs *xpcs)
244 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID1);
250 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID2);
258 xpcs->dev_flag = DW_DEV_TXGBE;
263 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev)
271 ret = xpcs_read(xpcs, dev, MDIO_CTRL1);
279 static int xpcs_soft_reset(struct dw_xpcs *xpcs,
298 ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET);
302 return xpcs_poll_reset(xpcs, dev);
311 static int xpcs_read_fault_c73(struct dw_xpcs *xpcs,
318 xpcs_warn(xpcs, state, "Link fault condition detected!\n");
322 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2);
327 xpcs_warn(xpcs, state, "Receiver fault detected!\n");
329 xpcs_warn(xpcs, state, "Transmitter fault detected!\n");
331 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS);
336 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n");
340 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1);
345 xpcs_warn(xpcs, state, "Link is not locked!\n");
347 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2);
352 xpcs_warn(xpcs, state, "Link has errors!\n");
359 static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed)
387 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
391 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN);
395 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
402 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
406 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
410 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST);
420 static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
438 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv);
451 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv);
462 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv);
465 static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
470 ret = _xpcs_config_aneg_c73(xpcs, compat);
474 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1);
480 return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret);
483 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs,
490 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA);
496 xpcs_config_aneg_c73(xpcs, compat);
506 static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs,
521 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i);
533 static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs,
587 static void xpcs_resolve_pma(struct dw_xpcs *xpcs,
598 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state);
611 struct dw_xpcs *xpcs;
614 xpcs = phylink_pcs_to_xpcs(pcs);
615 compat = xpcs_find_compat(xpcs->id, state->interface);
631 void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces)
636 const struct xpcs_compat *compat = &xpcs->id->compat[i];
644 int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable)
648 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0);
665 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret);
669 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1);
678 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret);
682 static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs,
687 if (xpcs->dev_flag == DW_DEV_TXGBE)
688 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, DW_CL37_BP | DW_EN_VSMMD1);
706 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
711 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
717 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
725 if (xpcs->dev_flag == DW_DEV_TXGBE) {
734 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
738 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
747 if (xpcs->dev_flag == DW_DEV_TXGBE)
750 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
755 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
761 static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs,
769 if (xpcs->dev_flag == DW_DEV_TXGBE)
770 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, DW_CL37_BP | DW_EN_VSMMD1);
777 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
782 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
788 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
793 if (!xpcs->pcs.poll)
795 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
805 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2,
814 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
819 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
828 static int xpcs_config_2500basex(struct dw_xpcs *xpcs)
832 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
837 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
841 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
847 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret);
850 int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
856 compat = xpcs_find_compat(xpcs->id, interface);
860 if (xpcs->dev_flag == DW_DEV_TXGBE) {
861 ret = txgbe_xpcs_switch_mode(xpcs, interface);
871 ret = xpcs_config_aneg_c73(xpcs, compat);
877 ret = xpcs_config_aneg_c37_sgmii(xpcs, neg_mode);
882 ret = xpcs_config_aneg_c37_1000basex(xpcs, neg_mode,
888 ret = xpcs_config_2500basex(xpcs);
897 ret = compat->pma_config(xpcs);
911 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
913 return xpcs_do_config(xpcs, interface, advertising, neg_mode);
916 static int xpcs_get_state_c73(struct dw_xpcs *xpcs,
929 pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
939 ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1);
941 ret = xpcs_soft_reset(xpcs, compat);
947 return xpcs_do_config(xpcs, state->interface, NULL,
962 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
968 state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat,
975 ret = xpcs_read_lpa_c73(xpcs, state, an_stat1);
983 xpcs_resolve_pma(xpcs, state);
989 static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
1003 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
1030 speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
1042 duplex = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE);
1051 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
1057 static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs,
1067 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA);
1071 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR);
1076 if (!xpcs->pcs.poll) {
1079 an_intr = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
1082 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, an_intr);
1092 static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs,
1097 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_STS);
1117 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1121 compat = xpcs_find_compat(xpcs->id, state->interface);
1127 phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state);
1130 ret = xpcs_get_state_c73(xpcs, state, compat);
1138 ret = xpcs_get_state_c37_sgmii(xpcs, state);
1145 ret = xpcs_get_state_c37_1000basex(xpcs, state);
1152 ret = xpcs_get_state_2500basex(xpcs, state);
1163 static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int neg_mode,
1172 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
1177 static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, unsigned int neg_mode,
1201 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
1209 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1212 return xpcs_config_usxgmii(xpcs, speed);
1214 return xpcs_link_up_sgmii(xpcs, neg_mode, speed, duplex);
1216 return xpcs_link_up_1000basex(xpcs, neg_mode, speed, duplex);
1222 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1225 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
1228 xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
1232 static u32 xpcs_get_id(struct dw_xpcs *xpcs)
1238 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1);
1244 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2);
1255 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1);
1261 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2);
1371 struct dw_xpcs *xpcs;
1375 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL);
1376 if (!xpcs)
1380 xpcs->mdiodev = mdiodev;
1382 xpcs_id = xpcs_get_id(xpcs);
1391 xpcs->id = entry;
1399 ret = xpcs_dev_flag(xpcs);
1403 xpcs->pcs.ops = &xpcs_phylink_ops;
1404 xpcs->pcs.neg_mode = true;
1406 if (xpcs->dev_flag != DW_DEV_TXGBE) {
1407 xpcs->pcs.poll = true;
1409 ret = xpcs_soft_reset(xpcs, compat);
1414 return xpcs;
1421 kfree(xpcs);
1426 void xpcs_destroy(struct dw_xpcs *xpcs)
1428 if (xpcs)
1429 mdio_device_put(xpcs->mdiodev);
1430 kfree(xpcs);
1438 struct dw_xpcs *xpcs;
1444 xpcs = xpcs_create(mdiodev, interface);
1454 return xpcs;