net/pcs/pcs-xpcs-wx.c

4 #include <linux/pcs/pcs-xpcs.h>
6 #include "pcs-xpcs.h"
49 static int txgbe_read_pma(struct dw_xpcs *xpcs, int reg)
51 	return xpcs_read(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg);
54 static int txgbe_write_pma(struct dw_xpcs *xpcs, int reg, u16 val)
56 	return xpcs_write(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, val);
59 static void txgbe_pma_config_10gbaser(struct dw_xpcs *xpcs)
63 	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x21);
64 	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0);
65 	val = txgbe_read_pma(xpcs, TXGBE_TX_GENCTL1);
67 	txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val);
68 	txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, TXGBE_MISC_CTL0_PLL |
70 	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_LD0, 0x549);
71 	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_REF0, 0x29);
72 	txgbe_write_pma(xpcs, TXGBE_TX_RATE_CTL, 0);
73 	txgbe_write_pma(xpcs, TXGBE_RX_RATE_CTL, 0);
74 	txgbe_write_pma(xpcs, TXGBE_TX_GEN_CTL2, TXGBE_TX_GEN_CTL2_TX0_WIDTH(3));
75 	txgbe_write_pma(xpcs, TXGBE_RX_GEN_CTL2, TXGBE_RX_GEN_CTL2_RX0_WIDTH(3));
76 	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL2, TXGBE_MPLLA_CTL2_DIV16P5_CLK_EN |
79 	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, TXGBE_RX_EQ_CTL0_CTLE_POLE(2) |
81 	val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL);
83 	txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);
84 	txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0xBE);
85 	val = txgbe_read_pma(xpcs, TXGBE_AFE_DFE_ENABLE);
87 	txgbe_write_pma(xpcs, TXGBE_AFE_DFE_ENABLE, val);
88 	val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_CTL4);
90 	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL4, val);
93 static void txgbe_pma_config_1g(struct dw_xpcs *xpcs)
97 	val = txgbe_read_pma(xpcs, TXGBE_TX_GENCTL1);
100 	txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val);
101 	txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, TXGBE_MISC_CTL0_PLL |
104 	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, TXGBE_RX_EQ_CTL0_VGA1_GAIN(7) |
106 	val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL);
108 	txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);
109 	txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0);
110 	val = txgbe_read_pma(xpcs, TXGBE_RX_GEN_CTL3);
112 	txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);
114 	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x20);
115 	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0x46);
116 	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_LD0, 0x540);
117 	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_REF0, 0x2A);
118 	txgbe_write_pma(xpcs, TXGBE_AFE_DFE_ENABLE, 0);
119 	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL4, TXGBE_RX_EQ_CTL4_CONT_OFF_CAN0);
120 	txgbe_write_pma(xpcs, TXGBE_TX_RATE_CTL, TXGBE_TX_RATE_CTL_TX0_RATE(3));
121 	txgbe_write_pma(xpcs, TXGBE_RX_RATE_CTL, TXGBE_RX_RATE_CTL_RX0_RATE(3));
122 	txgbe_write_pma(xpcs, TXGBE_TX_GEN_CTL2, TXGBE_TX_GEN_CTL2_TX0_WIDTH(1));
123 	txgbe_write_pma(xpcs, TXGBE_RX_GEN_CTL2, TXGBE_RX_GEN_CTL2_RX0_WIDTH(1));
124 	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL2, TXGBE_MPLLA_CTL2_DIV10_CLK_EN);
127 static int txgbe_pcs_poll_power_up(struct dw_xpcs *xpcs)
131 	/* Wait xpcs power-up good */
135 				xpcs, DW_VR_XS_PCS_DIG_STS);
137 		dev_err(&xpcs->mdiodev->dev, "xpcs power-up timeout\n");
142 static int txgbe_pma_init_done(struct dw_xpcs *xpcs)
146 	xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, DW_VR_RST | DW_EN_VSMMD1);
151 				xpcs, DW_VR_XS_PCS_DIG_CTRL1);
153 		dev_err(&xpcs->mdiodev->dev, "xpcs pma initialization timeout\n");
158 static bool txgbe_xpcs_mode_quirk(struct dw_xpcs *xpcs)
163 	ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_CTRL2);
166 	     xpcs->interface != PHY_INTERFACE_MODE_10GBASER) ||
167 	    xpcs->interface == PHY_INTERFACE_MODE_SGMII)
173 int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface)
186 	if (xpcs->interface == interface && !txgbe_xpcs_mode_quirk(xpcs))
189 	xpcs->interface = interface;
191 	ret = txgbe_pcs_poll_power_up(xpcs);
196 		xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBR);
197 		val = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1);
199 		xpcs_write(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, val);
200 		txgbe_pma_config_10gbaser(xpcs);
202 		xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBX);
203 		xpcs_write(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, 0);
204 		xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL1, 0);
205 		txgbe_pma_config_1g(xpcs);
208 	return txgbe_pma_init_done(xpcs);