Lines Matching refs:bc

260 #define tenms_to_flags(bc,tenms) ((tenms * bc->bitrate) / 800)
264 static inline void baycom_int_freq(struct baycom_state *bc)
271 bc->debug_vals.cur_intcnt++;
272 if (time_after_eq(cur_jiffies, bc->debug_vals.last_jiffies + HZ)) {
273 bc->debug_vals.last_jiffies = cur_jiffies;
274 bc->debug_vals.last_intcnt = bc->debug_vals.cur_intcnt;
275 bc->debug_vals.cur_intcnt = 0;
276 bc->debug_vals.last_pllcorr = bc->debug_vals.cur_pllcorr;
277 bc->debug_vals.cur_pllcorr = 0;
292 static int eppconfig(struct baycom_state *bc)
305 bc->cfg.intclk ? "int" : "ext",
306 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps,
307 (bc->cfg.fclk + 8 * bc->cfg.bps) / (16 * bc->cfg.bps),
308 bc->cfg.loopback ? ",loopback" : "");
309 sprintf(portarg, "%ld", bc->pdev->port->base);
317 static inline void do_kiss_params(struct baycom_state *bc,
331 bc->ch_params.tx_delay = data[1];
332 PKP("TX delay = %ums", 10 * bc->ch_params.tx_delay);
335 bc->ch_params.ppersist = data[1];
336 PKP("p persistence = %u", bc->ch_params.ppersist);
339 bc->ch_params.slottime = data[1];
340 PKP("slot time = %ums", bc->ch_params.slottime);
343 bc->ch_params.tx_tail = data[1];
344 PKP("TX tail = %ums", bc->ch_params.tx_tail);
347 bc->ch_params.fulldup = !!data[1];
348 PKP("%s duplex", bc->ch_params.fulldup ? "full" : "half");
358 static void encode_hdlc(struct baycom_state *bc)
367 if (bc->hdlctx.bufcnt > 0)
369 skb = bc->skb;
372 bc->skb = NULL;
374 wp = bc->hdlctx.buf;
412 bc->hdlctx.bufptr = bc->hdlctx.buf;
413 bc->hdlctx.bufcnt = wp - bc->hdlctx.buf;
415 bc->dev->stats.tx_packets++;
420 static int transmit(struct baycom_state *bc, int cnt, unsigned char stat)
422 struct parport *pp = bc->pdev->port;
426 if (bc->hdlctx.state == tx_tail && !(stat & EPP_PTTBIT))
427 bc->hdlctx.state = tx_idle;
428 if (bc->hdlctx.state == tx_idle && bc->hdlctx.calibrate <= 0) {
429 if (bc->hdlctx.bufcnt <= 0)
430 encode_hdlc(bc);
431 if (bc->hdlctx.bufcnt <= 0)
433 if (!bc->ch_params.fulldup) {
435 bc->hdlctx.slotcnt = bc->ch_params.slottime;
438 if ((--bc->hdlctx.slotcnt) > 0)
440 bc->hdlctx.slotcnt = bc->ch_params.slottime;
441 if (get_random_u8() > bc->ch_params.ppersist)
445 if (bc->hdlctx.state == tx_idle && bc->hdlctx.bufcnt > 0) {
446 bc->hdlctx.state = tx_keyup;
447 bc->hdlctx.flags = tenms_to_flags(bc, bc->ch_params.tx_delay);
448 bc->ptt_keyed++;
451 switch (bc->hdlctx.state) {
453 i = min_t(int, cnt, bc->hdlctx.flags);
455 bc->hdlctx.flags -= i;
456 if (bc->hdlctx.flags <= 0)
457 bc->hdlctx.state = tx_data;
468 if (bc->hdlctx.bufcnt <= 0) {
469 encode_hdlc(bc);
470 if (bc->hdlctx.bufcnt <= 0) {
471 bc->hdlctx.state = tx_tail;
472 bc->hdlctx.flags = tenms_to_flags(bc, bc->ch_params.tx_tail);
476 i = min_t(int, cnt, bc->hdlctx.bufcnt);
477 bc->hdlctx.bufcnt -= i;
479 if (i != pp->ops->epp_write_data(pp, bc->hdlctx.bufptr, i, 0))
481 bc->hdlctx.bufptr += i;
485 encode_hdlc(bc);
486 if (bc->hdlctx.bufcnt > 0) {
487 bc->hdlctx.state = tx_data;
490 i = min_t(int, cnt, bc->hdlctx.flags);
493 bc->hdlctx.flags -= i;
506 if (bc->hdlctx.calibrate <= 0)
508 i = min_t(int, cnt, bc->hdlctx.calibrate);
510 bc->hdlctx.calibrate -= i;
528 struct baycom_state *bc = netdev_priv(dev);
533 if (bc->hdlcrx.bufcnt < 4)
535 if (!check_crc_ccitt(bc->hdlcrx.buf, bc->hdlcrx.bufcnt))
537 pktlen = bc->hdlcrx.bufcnt-2+1; /* KISS kludge */
545 memcpy(cp, bc->hdlcrx.buf, pktlen - 1);
553 struct baycom_state *bc = netdev_priv(dev);
554 struct parport *pp = bc->pdev->port;
561 numbits = bc->hdlcrx.numbits;
562 state = bc->hdlcrx.state;
563 bitstream = bc->hdlcrx.bitstream;
564 bitbuf = bc->hdlcrx.bitbuf;
593 bc->hdlcrx.bufcnt = 0;
594 bc->hdlcrx.bufptr = bc->hdlcrx.buf;
607 if (bc->hdlcrx.bufcnt >= TXBUFFER_SIZE) {
610 *(bc->hdlcrx.bufptr)++ = bitbuf >> (16-numbits);
611 bc->hdlcrx.bufcnt++;
617 bc->hdlcrx.numbits = numbits;
618 bc->hdlcrx.state = state;
619 bc->hdlcrx.bitstream = bitstream;
620 bc->hdlcrx.bitbuf = bitbuf;
634 struct baycom_state *bc;
641 bc = container_of(work, struct baycom_state, run_work.work);
642 dev = bc->dev;
643 if (!bc->work_running)
645 baycom_int_freq(bc);
646 pp = bc->pdev->port;
650 bc->stat = stat;
651 bc->debug_vals.last_pllcorr = stat;
653 if (bc->modem == EPP_FPGAEXTSTATUS) {
674 if (transmit(bc, cnt2, stat))
681 bc->stat = stat;
701 if (transmit(bc, cnt, stat))
725 if (bc->bitrate < 50000)
727 else if (bc->bitrate < 100000)
739 bc->debug_vals.mod_cycles = time2 - time1;
740 bc->debug_vals.demod_cycles = time3 - time2;
742 schedule_delayed_work(&bc->run_work, 1);
743 if (!bc->skb)
757 struct baycom_state *bc = netdev_priv(dev);
763 do_kiss_params(bc, skb->data, skb->len);
767 if (bc->skb) {
777 bc->skb = skb;
797 struct baycom_state *bc = netdev_priv(dev);
800 if (!parport_claim(bc->pdev))
817 struct baycom_state *bc = netdev_priv(dev);
842 memset(&bc->modem, 0, sizeof(bc->modem));
857 bc->pdev = parport_register_dev_model(pp, dev->name, &par_cb, i);
859 if (!bc->pdev) {
863 if (parport_claim(bc->pdev)) {
865 parport_unregister_device(bc->pdev);
869 INIT_DELAYED_WORK(&bc->run_work, epp_bh);
870 bc->work_running = 1;
871 bc->modem = EPP_CONVENTIONAL;
872 if (eppconfig(bc))
875 bc->modem = /*EPP_FPGA*/ EPP_FPGAEXTSTATUS;
908 bc->bitrate = i * (8 * HZ) / tstart;
910 i = bc->bitrate >> 3;
916 bc_drvname, bc->bitrate, j, bc->bitrate >> (j+2));
923 bc->hdlcrx.state = 0;
924 bc->hdlcrx.numbits = 0;
925 bc->hdlctx.state = tx_idle;
926 bc->hdlctx.bufcnt = 0;
927 bc->hdlctx.slotcnt = bc->ch_params.slottime;
928 bc->hdlctx.calibrate = 0;
930 schedule_delayed_work(&bc->run_work, 1);
937 parport_release(bc->pdev);
938 parport_unregister_device(bc->pdev);
946 struct baycom_state *bc = netdev_priv(dev);
947 struct parport *pp = bc->pdev->port;
950 bc->work_running = 0;
951 cancel_delayed_work_sync(&bc->run_work);
952 bc->stat = EPP_DCDBIT;
956 parport_release(bc->pdev);
957 parport_unregister_device(bc->pdev);
958 dev_kfree_skb(bc->skb);
959 bc->skb = NULL;
967 static int baycom_setmode(struct baycom_state *bc, const char *modestr)
972 bc->cfg.intclk = 1;
974 bc->cfg.intclk = 0;
976 bc->cfg.extmodem = 0;
978 bc->cfg.extmodem = 1;
980 bc->cfg.loopback = 1;
982 bc->cfg.loopback = 0;
984 bc->cfg.fclk = simple_strtoul(cp+5, NULL, 0);
985 if (bc->cfg.fclk < 1000000)
986 bc->cfg.fclk = 1000000;
987 if (bc->cfg.fclk > 25000000)
988 bc->cfg.fclk = 25000000;
991 bc->cfg.bps = simple_strtoul(cp+4, NULL, 0);
992 if (bc->cfg.bps < 1000)
993 bc->cfg.bps = 1000;
994 if (bc->cfg.bps > 1500000)
995 bc->cfg.bps = 1500000;
1005 struct baycom_state *bc = netdev_priv(dev);
1018 hi.data.cp.tx_delay = bc->ch_params.tx_delay;
1019 hi.data.cp.tx_tail = bc->ch_params.tx_tail;
1020 hi.data.cp.slottime = bc->ch_params.slottime;
1021 hi.data.cp.ppersist = bc->ch_params.ppersist;
1022 hi.data.cp.fulldup = bc->ch_params.fulldup;
1028 bc->ch_params.tx_delay = hi.data.cp.tx_delay;
1029 bc->ch_params.tx_tail = hi.data.cp.tx_tail;
1030 bc->ch_params.slottime = hi.data.cp.slottime;
1031 bc->ch_params.ppersist = hi.data.cp.ppersist;
1032 bc->ch_params.fulldup = hi.data.cp.fulldup;
1033 bc->hdlctx.slotcnt = 1;
1055 hi.data.cs.ptt = !!(bc->stat & EPP_PTTBIT);
1056 hi.data.cs.dcd = !(bc->stat & EPP_DCDBIT);
1057 hi.data.cs.ptt_keyed = bc->ptt_keyed;
1065 hi.data.ocs.ptt = !!(bc->stat & EPP_PTTBIT);
1066 hi.data.ocs.dcd = !(bc->stat & EPP_DCDBIT);
1067 hi.data.ocs.ptt_keyed = bc->ptt_keyed;
1073 bc->hdlctx.calibrate = hi.data.calibrate * bc->bitrate / 8;
1082 bc->cfg.intclk ? "int" : "ext",
1083 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps,
1084 bc->cfg.loopback ? ",loopback" : "");
1091 return baycom_setmode(bc, hi.data.modename);
1129 struct baycom_state *bc;
1134 bc = netdev_priv(dev);
1138 bc->ch_params = dflt_ch_params;
1139 bc->ptt_keyed = 0;
1146 bc->skb = NULL;
1201 struct baycom_state *bc = netdev_priv(dev);
1206 bc->dev = dev;
1207 bc->magic = BAYCOM_MAGIC;
1208 bc->cfg.fclk = 19666600;
1209 bc->cfg.bps = 9600;
1276 struct baycom_state *bc = netdev_priv(dev);
1277 if (bc->magic == BAYCOM_MAGIC) {