ethernet/xilinx/xilinx_emaclite.c

110  * @base_addr:		base address of the Emaclite device
126 	void __iomem *base_addr;
155 	reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);
157 			 drvdata->base_addr + XEL_TSR_OFFSET);
160 	xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);
163 	xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
178 	xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
181 	reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);
183 			 drvdata->base_addr + XEL_TSR_OFFSET);
186 	reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET);
188 			 drvdata->base_addr + XEL_RSR_OFFSET);
314 	addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
379 	addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use);
472 	addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
642 	void __iomem *base_addr = lp->base_addr;
646 	if ((xemaclite_readl(base_addr + XEL_RSR_OFFSET) &
648 	    (xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)
654 	tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET);
658 		xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET);
664 	tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
668 		xemaclite_writel(tx_status, base_addr + XEL_BUFFER_OFFSET +
703 				  lp->base_addr + XEL_MDIOCTRL_OFFSET,
733 	ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
736 			 lp->base_addr + XEL_MDIOADDR_OFFSET);
738 			 lp->base_addr + XEL_MDIOCTRL_OFFSET);
743 	rc = xemaclite_readl(lp->base_addr + XEL_MDIORD_OFFSET);
782 	ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
785 			 lp->base_addr + XEL_MDIOADDR_OFFSET);
786 	xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET);
788 			 lp->base_addr + XEL_MDIOCTRL_OFFSET);
844 			 lp->base_addr + XEL_MDIOCTRL_OFFSET);
1117 	lp->base_addr = devm_platform_get_and_ioremap_resource(ofdev, 0, &res);
1118 	if (IS_ERR(lp->base_addr)) {
1119 		rc = PTR_ERR(lp->base_addr);
1139 	xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET);
1140 	xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
1165 		 (unsigned long __force)ndev->mem_start, lp->base_addr, ndev->irq);