wangxun/ngbe/ngbe_main.c

48  *  @wx: pointer to hardware structure
50 static void ngbe_init_type_code(struct wx *wx)
55 	wx->mac.type = wx_mac_em;
56 	type_mask = (u16)(wx->subsystem_device_id & NGBE_OEM_MASK);
57 	ncsi_mask = wx->subsystem_device_id & NGBE_NCSI_MASK;
58 	wol_mask = wx->subsystem_device_id & NGBE_WOL_MASK;
60 	val = rd32(wx, WX_CFG_PORT_ST);
61 	wx->mac_type = (val & BIT(7)) >> 7 ?
65 	wx->wol_hw_supported = (wol_mask == NGBE_WOL_SUP) ? 1 : 0;
66 	wx->ncsi_enabled = (ncsi_mask == NGBE_NCSI_MASK ||
74 		wx->gpio_ctrl = 1;
77 		wx->gpio_ctrl = 0;
84  * @wx: board private structure to initialize
86 static int ngbe_sw_init(struct wx *wx)
88 	struct pci_dev *pdev = wx->pdev;
92 	wx->mac.num_rar_entries = NGBE_RAR_ENTRIES;
93 	wx->mac.max_rx_queues = NGBE_MAX_RX_QUEUES;
94 	wx->mac.max_tx_queues = NGBE_MAX_TX_QUEUES;
95 	wx->mac.mcft_size = NGBE_MC_TBL_SIZE;
96 	wx->mac.vft_size = NGBE_SP_VFT_TBL_SIZE;
97 	wx->mac.rx_pb_size = NGBE_RX_PB_SIZE;
98 	wx->mac.tx_pb_size = NGBE_TDB_PB_SZ;
101 	err = wx_sw_init(wx);
106 	ngbe_init_type_code(wx);
109 	wx->max_q_vectors = NGBE_MAX_MSIX_VECTORS;
110 	err = wx_get_pcie_msix_counts(wx, &msix_count, NGBE_MAX_MSIX_VECTORS);
113 	wx->mac.max_msix_vectors = msix_count;
115 	wx->ring_feature[RING_F_RSS].limit = min_t(int, NGBE_MAX_RSS_INDICES,
117 	wx->rss_enabled = true;
120 	wx->rx_itr_setting = 1;
121 	wx->tx_itr_setting = 1;
124 	wx->tx_ring_count = NGBE_DEFAULT_TXD;
125 	wx->rx_ring_count = NGBE_DEFAULT_RXD;
128 	wx->tx_work_limit = NGBE_DEFAULT_TX_WORK;
129 	wx->rx_work_limit = NGBE_DEFAULT_RX_WORK;
136  * @wx: board private structure
139 static void ngbe_irq_enable(struct wx *wx, bool queues)
146 	wr32(wx, WX_GPIO_DDR, WX_GPIO_DDR_0);
147 	wr32(wx, WX_GPIO_INTEN, WX_GPIO_INTEN_0 | WX_GPIO_INTEN_1);
148 	wr32(wx, WX_GPIO_INTTYPE_LEVEL, 0x0);
149 	wr32(wx, WX_GPIO_POLARITY, wx->gpio_ctrl ? 0 : 0x3);
151 	wr32(wx, WX_PX_MISC_IEN, mask);
155 		wx_intr_enable(wx, NGBE_INTR_ALL);
157 		wx_intr_enable(wx, NGBE_INTR_MISC);
168 	struct wx *wx  = data;
172 	q_vector = wx->q_vector[0];
173 	pdev = wx->pdev;
175 	eicr = wx_misc_isb(wx, WX_ISB_VEC0);
180 		if (netif_running(wx->netdev))
181 			ngbe_irq_enable(wx, true);
184 	wx->isb_mem[WX_ISB_VEC0] = 0;
186 		wr32(wx, WX_PX_INTA, 1);
188 	wx->isb_mem[WX_ISB_MISC] = 0;
192 	if (netif_running(wx->netdev))
193 		ngbe_irq_enable(wx, false);
200 	struct wx *wx = data;
203 	if (netif_running(wx->netdev))
204 		ngbe_irq_enable(wx, false);
211  * @wx: board private structure
216 static int ngbe_request_msix_irqs(struct wx *wx)
218 	struct net_device *netdev = wx->netdev;
221 	for (vector = 0; vector < wx->num_q_vectors; vector++) {
222 		struct wx_q_vector *q_vector = wx->q_vector[vector];
223 		struct msix_entry *entry = &wx->msix_q_entries[vector];
235 			wx_err(wx, "request_irq failed for MSIX interrupt %s Error: %d\n",
241 	err = request_irq(wx->msix_entry->vector,
242 			  ngbe_msix_other, 0, netdev->name, wx);
245 		wx_err(wx, "request_irq for msix_other failed: %d\n", err);
254 		free_irq(wx->msix_q_entries[vector].vector,
255 			 wx->q_vector[vector]);
257 	wx_reset_interrupt_capability(wx);
263  * @wx: board private structure
268 static int ngbe_request_irq(struct wx *wx)
270 	struct net_device *netdev = wx->netdev;
271 	struct pci_dev *pdev = wx->pdev;
275 		err = ngbe_request_msix_irqs(wx);
278 				  netdev->name, wx);
281 				  netdev->name, wx);
284 		wx_err(wx, "request_irq failed, Error %d\n", err);
289 static void ngbe_disable_device(struct wx *wx)
291 	struct net_device *netdev = wx->netdev;
295 	for (i = 0; i < wx->num_rx_queues; i++)
297 		wx_disable_rx_queue(wx, wx->rx_ring[i]);
299 	wx_disable_rx(wx);
300 	wx_napi_disable_all(wx);
303 	if (wx->gpio_ctrl)
304 		ngbe_sfp_modules_txrx_powerctl(wx, false);
305 	wx_irq_disable(wx);
307 	for (i = 0; i < wx->num_tx_queues; i++) {
308 		u8 reg_idx = wx->tx_ring[i]->reg_idx;
310 		wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH);
313 	wx_update_stats(wx);
316 void ngbe_down(struct wx *wx)
318 	phylink_stop(wx->phylink);
319 	ngbe_disable_device(wx);
320 	wx_clean_all_tx_rings(wx);
321 	wx_clean_all_rx_rings(wx);
324 void ngbe_up(struct wx *wx)
326 	wx_configure_vectors(wx);
330 	wx_napi_enable_all(wx);
332 	netif_tx_start_all_queues(wx->netdev);
335 	rd32(wx, WX_PX_IC(0));
336 	rd32(wx, WX_PX_MISC_IC);
337 	ngbe_irq_enable(wx, true);
338 	if (wx->gpio_ctrl)
339 		ngbe_sfp_modules_txrx_powerctl(wx, true);
341 	phylink_start(wx->phylink);
355 	struct wx *wx = netdev_priv(netdev);
358 	wx_control_hw(wx, true);
360 	err = wx_setup_resources(wx);
364 	wx_configure(wx);
366 	err = ngbe_request_irq(wx);
370 	err = phylink_connect_phy(wx->phylink, wx->phydev);
374 	err = netif_set_real_num_tx_queues(netdev, wx->num_tx_queues);
378 	err = netif_set_real_num_rx_queues(netdev, wx->num_rx_queues);
382 	ngbe_up(wx);
386 	phylink_disconnect_phy(wx->phylink);
388 	wx_free_irq(wx);
390 	wx_free_resources(wx);
407 	struct wx *wx = netdev_priv(netdev);
409 	ngbe_down(wx);
410 	wx_free_irq(wx);
411 	wx_free_resources(wx);
412 	phylink_disconnect_phy(wx->phylink);
413 	wx_control_hw(wx, false);
420 	struct wx *wx = pci_get_drvdata(pdev);
422 	u32 wufc = wx->wol;
424 	netdev = wx->netdev;
430 	wx_clear_interrupt_scheme(wx);
435 		wx_configure_rx(wx);
436 		wr32(wx, NGBE_PSR_WKUP_CTL, wufc);
438 		wr32(wx, NGBE_PSR_WKUP_CTL, 0);
442 	wx_control_hw(wx, false);
449 	struct wx *wx = pci_get_drvdata(pdev);
452 	wake = !!wx->wol;
471 	struct wx *wx = netdev_priv(dev);
480 	wx_clear_interrupt_scheme(wx);
487 	wx_init_interrupt_scheme(wx);
516  * ngbe_probe initializes an wx identified by a pci_dev structure.
517  * The OS initialization, configuring of the wx private structure,
525 	struct wx *wx = NULL;
555 					 sizeof(struct wx),
565 	wx = netdev_priv(netdev);
566 	wx->netdev = netdev;
567 	wx->pdev = pdev;
568 	wx->msg_enable = BIT(3) - 1;
570 	wx->hw_addr = devm_ioremap(&pdev->dev,
573 	if (!wx->hw_addr) {
578 	wx->driver_name = ngbe_driver_name;
603 	wx->bd_number = func_nums;
605 	err = ngbe_sw_init(wx);
610 	err = wx_check_flash_load(wx, NGBE_SPI_ILDR_STATUS_PERST);
613 	err = wx_check_flash_load(wx, NGBE_SPI_ILDR_STATUS_PWRRST);
617 	err = wx_mng_present(wx);
623 	err = ngbe_reset_hw(wx);
629 	if (wx->bus.func == 0) {
630 		wr32(wx, NGBE_CALSUM_CAP_STATUS, 0x0);
631 		wr32(wx, NGBE_EEPROM_VERSION_STORE_REG, 0x0);
633 		e2rom_cksum_cap = rd32(wx, NGBE_CALSUM_CAP_STATUS);
634 		saved_ver = rd32(wx, NGBE_EEPROM_VERSION_STORE_REG);
637 	wx_init_eeprom_params(wx);
638 	if (wx->bus.func == 0 || e2rom_cksum_cap == 0) {
640 		err = ngbe_eeprom_chksum_hostif(wx);
648 	wx->wol = 0;
649 	if (wx->wol_hw_supported)
650 		wx->wol = NGBE_PSR_WKUP_CTL_MAG;
652 	netdev->wol_enabled = !!(wx->wol);
653 	wr32(wx, NGBE_PSR_WKUP_CTL, wx->wol);
654 	device_set_wakeup_enable(&pdev->dev, wx->wol);
662 		wx_read_ee_hostif(wx,
663 				  wx->eeprom.sw_region_offset + NGBE_EEPROM_VERSION_H,
666 		wx_read_ee_hostif(wx,
667 				  wx->eeprom.sw_region_offset + NGBE_EEPROM_VERSION_L,
670 		wr32(wx, NGBE_EEPROM_VERSION_STORE_REG, etrack_id);
672 	snprintf(wx->eeprom_id, sizeof(wx->eeprom_id),
675 	eth_hw_addr_set(netdev, wx->mac.perm_addr);
676 	wx_mac_set_default_filter(wx, wx->mac.perm_addr);
678 	err = wx_init_interrupt_scheme(wx);
683 	err = ngbe_mdio_init(wx);
691 	pci_set_drvdata(pdev, wx);
696 	phylink_destroy(wx->phylink);
697 	wx_control_hw(wx, false);
699 	wx_clear_interrupt_scheme(wx);
701 	kfree(wx->mac_table);
721 	struct wx *wx = pci_get_drvdata(pdev);
724 	netdev = wx->netdev;
726 	phylink_destroy(wx->phylink);
730 	kfree(wx->rss_key);
731 	kfree(wx->mac_table);
732 	wx_clear_interrupt_scheme(wx);
750 	struct wx *wx;
753 	wx = pci_get_drvdata(pdev);
754 	netdev = wx->netdev;
758 		wx_err(wx, "Cannot enable PCI device from suspend\n");
764 	ngbe_reset_hw(wx);
766 	err = wx_init_interrupt_scheme(wx);