ethernet/via/via-rhine.c

481 #define BYTE_REG_BITS_ON(x, p)      do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
489 #define BYTE_REG_BITS_OFF(x, p)     do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
493 #define BYTE_REG_BITS_SET(x, m, p)   do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
566 		iowrite8(mask >> 16, ioaddr + IntrStatus2);
582 		iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
585 		iowrite8(0x80, ioaddr + WOLcgClr);
588 		iowrite8(0xFF, ioaddr + WOLcrClr);
591 			iowrite8(0x03, ioaddr + WOLcrClr1);
599 		iowrite8(0xFF, ioaddr + PwrcsrClr);
601 			iowrite8(0x03, ioaddr + PwrcsrClr1);
636 	iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
644 			iowrite8(0x40, ioaddr + MiscCmd);
723 		iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
1356 	    iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1359 	    iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1396 	iowrite8(CAMC_CAMEN, ioaddr + CamCon);
1402 	iowrite8((u8) idx, ioaddr + CamAddr);
1405 		iowrite8(*addr, ioaddr + MulticastFilter0 + i);
1409 	iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
1412 	iowrite8(0, ioaddr + CamCon);
1425 	iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
1431 	iowrite8((u8) idx, ioaddr + CamAddr);
1437 	iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
1440 	iowrite8(0, ioaddr + CamCon);
1452 	iowrite8(CAMC_CAMEN, ioaddr + CamCon);
1459 	iowrite8(0, ioaddr + CamCon);
1471 	iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
1478 	iowrite8(0, ioaddr + CamCon);
1554 		iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1559 	iowrite8(0x20, ioaddr + TxConfig);
1585 	iowrite8(0, ioaddr + MIICmd);
1586 	iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1587 	iowrite8(0x80, ioaddr + MIICmd);
1591 	iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1599 	iowrite8(0, ioaddr + MIICmd);
1602 		iowrite8(0x01, ioaddr + MIIRegAddr);	// MII_BMSR
1608 		iowrite8(0x80, ioaddr + MIICmd);
1613 		iowrite8(0, ioaddr + MIICmd);
1630 	iowrite8(phy_id, ioaddr + MIIPhyAddr);
1631 	iowrite8(regnum, ioaddr + MIIRegAddr);
1632 	iowrite8(0x40, ioaddr + MIICmd);		/* Trigger read */
1648 	iowrite8(phy_id, ioaddr + MIIPhyAddr);
1649 	iowrite8(regnum, ioaddr + MIIRegAddr);
1651 	iowrite8(0x20, ioaddr + MIICmd);		/* Trigger write */
1858 	iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
2161 		iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
2168 		iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
2416 	iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
2471 		iowrite8(0x04, ioaddr + WOLcgClr);
2476 		iowrite8(WOLmagic, ioaddr + WOLcrSet);
2481 		iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
2485 		iowrite8(WOLbmcast, ioaddr + WOLcgSet);
2488 		iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
2491 		iowrite8(WOLucast, ioaddr + WOLcrSet);
2495 		iowrite8(0x01, ioaddr + PwcfgSet);
2496 		iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
2502 		iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);