Lines Matching defs:access
78 u32 access;
130 * In the worst case, we could be kicking off a user-access immediately
132 * so, our request could get deferred by one access cycle. We
133 * defensively allow for 4 access cycles.
358 /* wait until hardware is ready for another user access */
366 reg = readl(®s->user[0].access);
386 reg = readl(®s->user[0].access);
390 dev_err(data->dev, "timed out waiting for user access\n");
431 writel(reg, &data->regs->user[0].access);
439 reg = readl(&data->regs->user[0].access);
473 writel(reg, &data->regs->user[0].access);