ethernet/synopsys/dwc-xlgmac-hw.c

41 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS,
53 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS,
98 		mac_addr_hi = XLGMAC_SET_REG_BITS(mac_addr_hi,
116 	regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLRXS_POS,
119 	regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_DOVLTC_POS,
122 	regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ERSVLM_POS,
125 	regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ESVL_POS,
128 	regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLS_POS,
140 	regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLS_POS,
153 	regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_VTFE_POS,
159 	regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VTHM_POS,
162 	regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VTIM_POS,
165 	regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ETV_POS,
173 	regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VL_POS,
186 	regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_VTFE_POS,
236 	regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANHTR_VLHT_POS,
258 	regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_PR_POS,
288 	regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_PM_POS,
382 		regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HPF_POS,
384 		regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HUC_POS,
386 		regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HMC_POS,
400 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_JE_POS,
419 	regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANIR_CSVL_POS,
421 	regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANIR_VLTI_POS,
510 		regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_ST_POS,
518 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TXQEN_POS,
526 	regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_TE_POS,
548 	regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_TE_POS,
555 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TXQEN_POS,
567 		regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_ST_POS,
614 		regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_SR_POS,
627 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_DCRCC_POS,
629 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_CST_POS,
631 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_ACS_POS,
633 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_RE_POS,
646 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_DCRCC_POS,
648 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_CST_POS,
650 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_ACS_POS,
652 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_RE_POS,
670 		regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_SR_POS,
1028 			pkt_info->attributes = XLGMAC_SET_REG_BITS(
1197 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_EHFC_POS,
1208 		regval = XLGMAC_SET_REG_BITS(regval,
1229 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_EHFC_POS,
1242 		regval = XLGMAC_SET_REG_BITS(regval, MAC_Q0TFCR_TFE_POS,
1245 		regval = XLGMAC_SET_REG_BITS(regval, MAC_Q0TFCR_PT_POS,
1261 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RFCR_RFE_POS,
1273 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RFCR_RFE_POS,
1312 		regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RIWT_RWT_POS,
1334 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_FEP_POS,
1347 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_FUP_POS,
1370 		regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_RBSZ_POS,
1390 			regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_TSE_POS,
1409 		regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_CR_SPH_POS,
1415 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_HDSMS_POS,
1465 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RTC_POS,
1480 	regval = XLGMAC_SET_REG_BITS(regval, MTL_OMR_ETSALG_POS,
1487 		regval = XLGMAC_SET_REG_BITS(regval, MTL_TC_ETSCR_TSA_POS,
1492 		regval = XLGMAC_SET_REG_BITS(regval, MTL_TC_QWR_QW_POS,
1499 	regval = XLGMAC_SET_REG_BITS(regval, MTL_OMR_RAA_POS,
1524 			regval = XLGMAC_SET_REG_BITS(regval,
1538 			regval = XLGMAC_SET_REG_BITS(regval,
1642 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TQS_POS,
1664 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RQS_POS,
1682 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQFCR_RFA_POS,
1685 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQFCR_RFD_POS,
1699 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TTC_POS,
1715 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RSF_POS,
1731 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TSF_POS,
1751 		regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_OSP_POS,
1769 		regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_CR_PBLX8_POS,
1800 		regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_PBL_POS,
1831 		regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_PBL_POS,
2131 	regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_MCF_POS,
2260 	regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_MCF_POS,
2271 	regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_ROR_POS,
2274 	regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_CR_POS,
2298 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_RSSIA_POS,
2300 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_ADDRT_POS,
2302 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_CT_POS,
2304 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_OB_POS,
2374 		pdata->rss_table[i] = XLGMAC_SET_REG_BITS(
2407 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSCR_RSSE_POS,
2422 	regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSCR_RSSE_POS,
2466 		dma_ch_ier = XLGMAC_SET_REG_BITS(dma_ch_ier,
2469 		dma_ch_ier = XLGMAC_SET_REG_BITS(dma_ch_ier,
2472 		dma_ch_ier = XLGMAC_SET_REG_BITS(dma_ch_ier,
2482 				dma_ch_ier = XLGMAC_SET_REG_BITS(
2494 			dma_ch_ier = XLGMAC_SET_REG_BITS(
2500 				dma_ch_ier = XLGMAC_SET_REG_BITS(
2533 	mac_ier = XLGMAC_SET_REG_BITS(mac_ier, MAC_IER_TSIE_POS,
2540 	regval = XLGMAC_SET_REG_BITS(regval, MMC_RIER_ALL_INTERRUPTS_POS,
2544 	regval = XLGMAC_SET_REG_BITS(regval, MMC_TIER_ALL_INTERRUPTS_POS,
2559 	regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,
2576 	regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,
2593 	regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,
2610 	regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS,
2670 		pkt_info->attributes = XLGMAC_SET_REG_BITS(
2675 		pkt_info->attributes = XLGMAC_SET_REG_BITS(
2684 	pkt_info->attributes = XLGMAC_SET_REG_BITS(
2694 		pkt_info->attributes = XLGMAC_SET_REG_BITS(
2715 		pkt_info->attributes = XLGMAC_SET_REG_BITS(
2747 		pkt_info->attributes = XLGMAC_SET_REG_BITS(
2756 	pkt_info->attributes = XLGMAC_SET_REG_BITS(
2764 		pkt_info->attributes = XLGMAC_SET_REG_BITS(
2783 			pkt_info->attributes = XLGMAC_SET_REG_BITS(
2797 			pkt_info->attributes = XLGMAC_SET_REG_BITS(
2803 			pkt_info->errors = XLGMAC_SET_REG_BITS(
2825 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2830 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2835 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2840 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2845 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2850 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2855 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2858 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2863 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2888 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2893 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2898 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2903 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2908 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2913 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2918 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2921 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2926 		dma_ch_ier = XLGMAC_SET_REG_BITS(
2950 		regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_FTQ_POS,
2977 	regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_EAME_POS,
2980 	regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_UNDEF_POS,
2982 	regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_BLEN_256_POS,
3048 	regval = XLGMAC_SET_REG_BITS(regval, DMA_MR_SWR_POS,