Lines Matching defs:hp
104 static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
112 tlp->tx_new = hp->tx_new;
113 tlp->tx_old = hp->tx_old;
133 #define tx_add_log(hp, a, s)
252 static inline u32 hme_read_desc32(struct happy_meal *hp, hme32 *p)
261 static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
263 hme_write32(hp, tregs + TCVR_BBDATA, bit);
264 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
265 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
269 static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
273 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
274 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
275 ret = hme_read32(hp, tregs + TCVR_CFG);
285 static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
289 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
291 retval = hme_read32(hp, tregs + TCVR_CFG);
296 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
303 static int happy_meal_bb_read(struct happy_meal *hp,
311 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
315 BB_PUT_BIT(hp, tregs, 1);
318 BB_PUT_BIT(hp, tregs, 0);
319 BB_PUT_BIT(hp, tregs, 1);
320 BB_PUT_BIT(hp, tregs, 1);
321 BB_PUT_BIT(hp, tregs, 0);
324 tmp = hp->paddr & 0xff;
326 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
331 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
334 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
337 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
339 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
340 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
341 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
342 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
347 static void happy_meal_bb_write(struct happy_meal *hp,
357 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
361 BB_PUT_BIT(hp, tregs, 1);
364 BB_PUT_BIT(hp, tregs, 0);
365 BB_PUT_BIT(hp, tregs, 1);
366 BB_PUT_BIT(hp, tregs, 0);
367 BB_PUT_BIT(hp, tregs, 1);
370 tmp = (hp->paddr & 0xff);
372 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
377 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
380 BB_PUT_BIT(hp, tregs, 1);
381 BB_PUT_BIT(hp, tregs, 0);
384 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
387 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
392 static int happy_meal_tcvr_read(struct happy_meal *hp,
398 if (hp->tcvr_type == none) {
403 if (!(hp->happy_flags & HFLAG_FENABLE)) {
405 return happy_meal_bb_read(hp, tregs, reg);
408 hme_write32(hp, tregs + TCVR_FRAME,
409 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
410 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
413 netdev_err(hp->dev, "Aieee, transceiver MIF read bolixed\n");
416 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
423 static void happy_meal_tcvr_write(struct happy_meal *hp,
432 if (!(hp->happy_flags & HFLAG_FENABLE)) {
433 happy_meal_bb_write(hp, tregs, reg, value);
438 hme_write32(hp, tregs + TCVR_FRAME,
439 (FRAME_WRITE | (hp->paddr << 23) |
441 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
446 netdev_err(hp->dev, "Aieee, transceiver MIF write bolixed\n");
483 static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
485 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
490 if (hp->sw_bmcr & BMCR_FULLDPLX) {
491 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
492 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
497 if (hp->sw_bmcr & BMCR_SPEED100) {
498 hp->sw_bmcr &= ~(BMCR_SPEED100);
499 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
507 static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
509 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
511 netdev_info(hp->dev,
513 hp->tcvr_type == external ? "external" : "internal",
514 hp->sw_lpa & (LPA_100HALF | LPA_100FULL) ? 100 : 10,
515 hp->sw_lpa & (LPA_100FULL | LPA_10FULL) ? "Full" : "Half");
518 static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
520 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
522 netdev_info(hp->dev,
524 hp->tcvr_type == external ? "external" : "internal",
525 hp->sw_bmcr & BMCR_SPEED100 ? 100 : 10,
526 hp->sw_bmcr & BMCR_FULLDPLX ? "Full" : "Half");
529 static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
536 if (hp->timer_state == arbwait) {
537 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
538 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
540 if (hp->sw_lpa & LPA_100FULL)
542 else if (hp->sw_lpa & LPA_100HALF)
544 else if (hp->sw_lpa & LPA_10FULL)
550 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
551 if (hp->sw_bmcr & BMCR_FULLDPLX)
565 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
566 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
568 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
571 hp->happy_flags |= HFLAG_FULL;
572 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
573 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
576 hp->happy_flags &= ~(HFLAG_FULL);
577 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
578 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
581 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
582 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
589 static int is_lucent_phy(struct happy_meal *hp)
591 void __iomem *tregs = hp->tcvregs;
595 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
596 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
604 /* hp->happy_lock must be held */
606 happy_meal_begin_auto_negotiation(struct happy_meal *hp,
613 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
614 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
615 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
616 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
620 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
623 if (hp->sw_bmsr & BMSR_10HALF)
624 hp->sw_advertise |= (ADVERTISE_10HALF);
626 hp->sw_advertise &= ~(ADVERTISE_10HALF);
628 if (hp->sw_bmsr & BMSR_10FULL)
629 hp->sw_advertise |= (ADVERTISE_10FULL);
631 hp->sw_advertise &= ~(ADVERTISE_10FULL);
632 if (hp->sw_bmsr & BMSR_100HALF)
633 hp->sw_advertise |= (ADVERTISE_100HALF);
635 hp->sw_advertise &= ~(ADVERTISE_100HALF);
636 if (hp->sw_bmsr & BMSR_100FULL)
637 hp->sw_advertise |= (ADVERTISE_100FULL);
639 hp->sw_advertise &= ~(ADVERTISE_100FULL);
640 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
649 hp->sw_advertise & ADVERTISE_10HALF ? "10H " : "",
650 hp->sw_advertise & ADVERTISE_10FULL ? "10F " : "",
651 hp->sw_advertise & ADVERTISE_100HALF ? "100H " : "",
652 hp->sw_advertise & ADVERTISE_100FULL ? "100F " : "");
655 hp->sw_bmcr |= BMCR_ANENABLE;
656 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
659 hp->sw_bmcr |= BMCR_ANRESTART;
660 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
666 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
667 if (!(hp->sw_bmcr & BMCR_ANRESTART))
672 netdev_err(hp->dev,
674 hp->sw_bmcr);
675 netdev_notice(hp->dev,
679 hp->timer_state = arbwait;
692 hp->sw_bmcr = BMCR_SPEED100;
695 hp->sw_bmcr = BMCR_SPEED100;
697 hp->sw_bmcr = 0;
699 hp->sw_bmcr |= BMCR_FULLDPLX;
701 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
703 if (!is_lucent_phy(hp)) {
708 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
710 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
711 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
712 hp->sw_csconfig);
714 hp->timer_state = ltrywait;
717 hp->timer_ticks = 0;
718 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
719 add_timer(&hp->happy_timer);
724 struct happy_meal *hp = from_timer(hp, t, happy_timer);
725 void __iomem *tregs = hp->tcvregs;
728 spin_lock_irq(&hp->happy_lock);
730 hp->timer_ticks++;
731 switch(hp->timer_state) {
736 if (hp->timer_ticks >= 10) {
739 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
740 netdev_notice(hp->dev,
742 hp->sw_bmcr = BMCR_SPEED100;
743 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
745 if (!is_lucent_phy(hp)) {
750 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
751 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
752 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
754 hp->timer_state = ltrywait;
755 hp->timer_ticks = 0;
759 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
760 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
764 ret = set_happy_link_modes(hp, tregs);
776 hp->timer_state = lupwait;
790 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
791 if (hp->sw_bmsr & BMSR_LSTATUS) {
795 display_link_mode(hp, tregs);
796 hp->timer_state = asleep;
799 if (hp->timer_ticks >= 10) {
800 netdev_notice(hp->dev,
802 hp->timer_ticks = 0;
816 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
817 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
818 if (hp->timer_ticks == 1) {
819 if (!is_lucent_phy(hp)) {
823 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
824 happy_meal_tcvr_write(hp, tregs,
825 DP83840_CSCONFIG, hp->sw_csconfig);
830 if (hp->timer_ticks == 2) {
831 if (!is_lucent_phy(hp)) {
832 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
833 happy_meal_tcvr_write(hp, tregs,
834 DP83840_CSCONFIG, hp->sw_csconfig);
839 if (hp->sw_bmsr & BMSR_LSTATUS) {
841 display_forced_link_mode(hp, tregs);
842 set_happy_link_modes(hp, tregs); /* XXX error? then what? */
843 hp->timer_state = asleep;
846 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
849 ret = try_next_permutation(hp, tregs);
856 netdev_notice(hp->dev,
859 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
862 if (!is_lucent_phy(hp)) {
863 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
865 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
866 happy_meal_tcvr_write(hp, tregs,
867 DP83840_CSCONFIG, hp->sw_csconfig);
869 hp->timer_ticks = 0;
880 netdev_err(hp->dev,
883 hp->timer_ticks = 0;
884 hp->timer_state = asleep; /* foo on you */
889 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
890 add_timer(&hp->happy_timer);
894 spin_unlock_irq(&hp->happy_lock);
900 /* hp->happy_lock must be held */
901 static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
908 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
909 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
914 netdev_err(hp->dev, "Transceiver BigMac ATTACK!");
920 /* hp->happy_lock must be held */
921 static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
928 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
929 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
934 netdev_err(hp->dev, "Receiver BigMac ATTACK!\n");
942 /* hp->happy_lock must be held */
943 static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
950 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
951 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
956 netdev_err(hp->dev, "Fry guys.\n");
962 /* hp->happy_lock must be held */
963 static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
965 struct net_device_stats *stats = &hp->dev->stats;
967 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
968 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
970 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
971 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
973 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
974 hme_write32(hp, bregs + BMAC_GLECTR, 0);
976 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
979 (hme_read32(hp, bregs + BMAC_EXCTR) +
980 hme_read32(hp, bregs + BMAC_LTCTR));
981 hme_write32(hp, bregs + BMAC_EXCTR, 0);
982 hme_write32(hp, bregs + BMAC_LTCTR, 0);
991 /* hp->happy_lock must be held */
992 static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
997 tconfig = hme_read32(hp, tregs + TCVR_CFG);
999 if (hp->tcvr_type == external) {
1000 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1001 hp->tcvr_type = internal;
1002 hp->paddr = TCV_PADDR_ITX;
1003 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1005 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1011 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1012 hp->tcvr_type = external;
1013 hp->paddr = TCV_PADDR_ETX;
1016 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1017 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1019 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1025 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1026 hp->tcvr_type = internal;
1027 hp->paddr = TCV_PADDR_ITX;
1032 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1035 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1038 hp->sw_bmcr = result;
1050 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1051 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1052 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1053 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1056 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1057 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1061 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1073 if (!is_lucent_phy(hp)) {
1074 result = happy_meal_tcvr_read(hp, tregs,
1076 happy_meal_tcvr_write(hp, tregs,
1084 * hp->happy_lock must be held
1086 static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
1088 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1089 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1093 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1094 hp->paddr = TCV_PADDR_ETX;
1095 hp->tcvr_type = external;
1099 hme_write32(hp, tregs + TCVR_CFG,
1101 hp->paddr = TCV_PADDR_ITX;
1102 hp->tcvr_type = internal;
1105 netdev_err(hp->dev,
1107 hp->tcvr_type = none; /* Grrr... */
1157 static void happy_meal_clean_rings(struct happy_meal *hp)
1162 if (hp->rx_skbs[i] != NULL) {
1163 struct sk_buff *skb = hp->rx_skbs[i];
1167 rxd = &hp->happy_block->happy_meal_rxd[i];
1168 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1169 dma_unmap_single(hp->dma_dev, dma_addr,
1172 hp->rx_skbs[i] = NULL;
1177 if (hp->tx_skbs[i] != NULL) {
1178 struct sk_buff *skb = hp->tx_skbs[i];
1183 hp->tx_skbs[i] = NULL;
1186 txd = &hp->happy_block->happy_meal_txd[i];
1187 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1189 dma_unmap_single(hp->dma_dev, dma_addr,
1190 (hme_read_desc32(hp, &txd->tx_flags)
1194 dma_unmap_page(hp->dma_dev, dma_addr,
1195 (hme_read_desc32(hp, &txd->tx_flags)
1208 /* hp->happy_lock must be held */
1209 static void happy_meal_init_rings(struct happy_meal *hp)
1211 struct hmeal_init_block *hb = hp->happy_block;
1215 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1218 happy_meal_clean_rings(hp);
1228 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1231 hp->rx_skbs[i] = skb;
1235 mapping = dma_map_single(hp->dma_dev, skb->data, RX_BUF_ALLOC_SIZE,
1237 if (dma_mapping_error(hp->dma_dev, mapping)) {
1239 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1242 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1250 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1255 /* hp->happy_lock must be held */
1256 static int happy_meal_init(struct happy_meal *hp)
1258 const unsigned char *e = &hp->dev->dev_addr[0];
1259 void __iomem *gregs = hp->gregs;
1260 void __iomem *etxregs = hp->etxregs;
1261 void __iomem *erxregs = hp->erxregs;
1262 void __iomem *bregs = hp->bigmacregs;
1263 void __iomem *tregs = hp->tcvregs;
1268 del_timer(&hp->happy_timer);
1270 HMD("happy_flags[%08x]\n", hp->happy_flags);
1271 if (!(hp->happy_flags & HFLAG_INIT)) {
1273 hp->happy_flags |= HFLAG_INIT;
1274 happy_meal_get_counters(hp, bregs);
1279 happy_meal_stop(hp, gregs);
1283 happy_meal_init_rings(hp);
1286 if (hp->happy_flags & HFLAG_FENABLE) {
1288 hme_read32(hp, tregs + TCVR_CFG));
1289 hme_write32(hp, tregs + TCVR_CFG,
1290 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1293 hme_read32(hp, tregs + TCVR_CFG));
1294 hme_write32(hp, tregs + TCVR_CFG,
1295 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1300 happy_meal_transceiver_check(hp, tregs);
1303 switch(hp->tcvr_type) {
1312 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1318 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1322 if (happy_meal_tcvr_reset(hp, tregs))
1327 happy_meal_tx_reset(hp, bregs);
1328 happy_meal_rx_reset(hp, bregs);
1331 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1332 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1333 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1338 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1340 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1341 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1342 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1344 if ((hp->dev->flags & IFF_ALLMULTI) ||
1345 (netdev_mc_count(hp->dev) > 64)) {
1346 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1347 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1348 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1349 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1350 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1356 netdev_for_each_mc_addr(ha, hp->dev) {
1361 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1362 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1363 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1364 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1366 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1367 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1368 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1369 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1374 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1375 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1376 hme_write32(hp, erxregs + ERX_RING,
1377 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1378 hme_write32(hp, etxregs + ETX_RING,
1379 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1386 if (hme_read32(hp, erxregs + ERX_RING) !=
1387 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1388 hme_write32(hp, erxregs + ERX_RING,
1389 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1395 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1397 if ((hp->happy_bursts & DMA_BURST64) &&
1398 ((hp->happy_flags & HFLAG_PCI) != 0
1410 if ((hp->happy_flags & HFLAG_PCI) == 0) {
1411 struct platform_device *op = hp->happy_dev;
1414 hp->happy_bursts);
1421 hme_write32(hp, gregs + GREG_CFG, gcfg);
1422 } else if (hp->happy_bursts & DMA_BURST32) {
1424 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1425 } else if (hp->happy_bursts & DMA_BURST16) {
1427 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1430 hme_write32(hp, gregs + GREG_CFG, 0);
1435 hme_read32(hp, gregs + GREG_CFG), bursts);
1438 hme_write32(hp, gregs + GREG_IMASK,
1444 hme_read32(hp, etxregs + ETX_RSIZE));
1445 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1448 HMD("tx dma enable old[%08x]\n", hme_read32(hp, etxregs + ETX_CFG));
1449 hme_write32(hp, etxregs + ETX_CFG,
1450 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1458 hme_read32(hp, erxregs + ERX_CFG));
1459 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1460 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1461 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1462 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1463 netdev_err(hp->dev,
1465 netdev_err(hp->dev,
1473 hme_read32(hp, bregs + BMAC_RXCFG));
1475 if (hp->dev->flags & IFF_PROMISC)
1477 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1485 if (hp->happy_flags & HFLAG_FULL)
1491 hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/);
1494 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1500 if (hp->happy_flags & HFLAG_LANCE)
1504 if (hp->tcvr_type == external)
1507 HMD("XIF config old[%08x]\n", hme_read32(hp, bregs + BMAC_XIFCFG));
1508 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1512 hme_read32(hp, bregs + BMAC_TXCFG),
1513 hme_read32(hp, bregs + BMAC_RXCFG));
1516 hme_write32(hp, bregs + BMAC_TXMAX, ETH_FRAME_LEN + 8);
1517 hme_write32(hp, bregs + BMAC_RXMAX, ETH_FRAME_LEN + 8);
1519 hme_write32(hp, bregs + BMAC_TXCFG,
1520 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1521 hme_write32(hp, bregs + BMAC_RXCFG,
1522 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1525 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1531 /* hp->happy_lock must be held */
1532 static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1534 void __iomem *tregs = hp->tcvregs;
1535 void __iomem *bregs = hp->bigmacregs;
1536 void __iomem *gregs = hp->gregs;
1538 happy_meal_stop(hp, gregs);
1539 if (hp->happy_flags & HFLAG_FENABLE)
1540 hme_write32(hp, tregs + TCVR_CFG,
1541 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1543 hme_write32(hp, tregs + TCVR_CFG,
1544 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1545 happy_meal_transceiver_check(hp, tregs);
1546 switch(hp->tcvr_type) {
1550 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1553 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1556 if (happy_meal_tcvr_reset(hp, tregs))
1560 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1561 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1564 if (hp->sw_bmsr & BMSR_10HALF)
1565 hp->sw_advertise |= (ADVERTISE_10HALF);
1567 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1569 if (hp->sw_bmsr & BMSR_10FULL)
1570 hp->sw_advertise |= (ADVERTISE_10FULL);
1572 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1573 if (hp->sw_bmsr & BMSR_100HALF)
1574 hp->sw_advertise |= (ADVERTISE_100HALF);
1576 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1577 if (hp->sw_bmsr & BMSR_100FULL)
1578 hp->sw_advertise |= (ADVERTISE_100FULL);
1580 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1583 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1589 * hp->happy_lock must be held
1591 static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1602 netdev_err(hp->dev,
1609 netdev_dbg(hp->dev, "Happy Meal receive FIFO overflow.\n");
1614 netdev_err(hp->dev, "Happy Meal BigMAC SQE test failed.\n");
1620 netdev_err(hp->dev,
1629 netdev_err(hp->dev, "Happy Meal MAX Packet size error.\n");
1639 netdev_info(hp->dev,
1645 netdev_err(hp->dev, "Happy Meal rx DMA errors [ %s%s%s]\n",
1656 netdev_err(hp->dev,
1663 netdev_err(hp->dev, "Happy Meal MIF interrupt.\n");
1669 netdev_err(hp->dev, "Happy Meal tx DMA errors [ %s%s%s%s]\n",
1681 netdev_err(hp->dev,
1688 netdev_notice(hp->dev, "Resetting...\n");
1689 happy_meal_init(hp);
1695 /* hp->happy_lock must be held */
1696 static void happy_meal_tx(struct happy_meal *hp)
1698 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1700 struct net_device *dev = hp->dev;
1703 elem = hp->tx_old;
1704 while (elem != hp->tx_new) {
1709 netdev_vdbg(hp->dev, "TX[%d]\n", elem);
1711 flags = hme_read_desc32(hp, &this->tx_flags);
1714 skb = hp->tx_skbs[elem];
1720 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1724 hp->tx_skbs[elem] = NULL;
1728 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1729 dma_len = hme_read_desc32(hp, &this->tx_flags);
1733 dma_unmap_single(hp->dma_dev, dma_addr, dma_len, DMA_TO_DEVICE);
1735 dma_unmap_page(hp->dma_dev, dma_addr, dma_len, DMA_TO_DEVICE);
1744 hp->tx_old = elem;
1747 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
1758 * hp->happy_lock must be held
1760 static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
1762 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
1764 int elem = hp->rx_new, drops = 0;
1768 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
1772 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
1788 hme_write_rxd(hp, this,
1793 skb = hp->rx_skbs[elem];
1805 mapping = dma_map_single(hp->dma_dev, new_skb->data,
1808 if (unlikely(dma_mapping_error(hp->dma_dev, mapping))) {
1814 dma_unmap_single(hp->dma_dev, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE);
1815 hp->rx_skbs[elem] = new_skb;
1816 hme_write_rxd(hp, this,
1833 dma_sync_single_for_cpu(hp->dma_dev, dma_addr, len + 2, DMA_FROM_DEVICE);
1835 dma_sync_single_for_device(hp->dma_dev, dma_addr, len + 2, DMA_FROM_DEVICE);
1837 hme_write_rxd(hp, this,
1858 hp->rx_new = elem;
1860 netdev_info(hp->dev, "Memory squeeze, deferring packet.\n");
1866 struct happy_meal *hp = netdev_priv(dev);
1867 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
1873 spin_lock(&hp->happy_lock);
1876 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
1881 happy_meal_tx(hp);
1884 happy_meal_rx(hp, dev);
1888 spin_unlock(&hp->happy_lock);
1895 struct happy_meal *hp = netdev_priv(dev);
1898 res = request_irq(hp->irq, happy_meal_interrupt, IRQF_SHARED,
1901 netdev_err(dev, "Can't order irq %d to go.\n", hp->irq);
1907 spin_lock_irq(&hp->happy_lock);
1908 res = happy_meal_init(hp);
1909 spin_unlock_irq(&hp->happy_lock);
1912 free_irq(hp->irq, dev);
1918 struct happy_meal *hp = netdev_priv(dev);
1920 spin_lock_irq(&hp->happy_lock);
1921 happy_meal_stop(hp, hp->gregs);
1922 happy_meal_clean_rings(hp);
1925 del_timer(&hp->happy_timer);
1927 spin_unlock_irq(&hp->happy_lock);
1929 free_irq(hp->irq, dev);
1936 struct happy_meal *hp = netdev_priv(dev);
1941 hme_read32(hp, hp->gregs + GREG_STAT),
1942 hme_read32(hp, hp->etxregs + ETX_CFG),
1943 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
1945 spin_lock_irq(&hp->happy_lock);
1946 happy_meal_init(hp);
1947 spin_unlock_irq(&hp->happy_lock);
1952 static void unmap_partial_tx_skb(struct happy_meal *hp, u32 first_mapping,
1955 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1957 dma_unmap_single(hp->dma_dev, first_mapping, first_len, DMA_TO_DEVICE);
1964 addr = hme_read_desc32(hp, &this->tx_addr);
1965 len = hme_read_desc32(hp, &this->tx_flags);
1967 dma_unmap_page(hp->dma_dev, addr, len, DMA_TO_DEVICE);
1974 struct happy_meal *hp = netdev_priv(dev);
1988 spin_lock_irq(&hp->happy_lock);
1990 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
1992 spin_unlock_irq(&hp->happy_lock);
1997 entry = hp->tx_new;
1999 hp->tx_skbs[entry] = skb;
2005 mapping = dma_map_single(hp->dma_dev, skb->data, len, DMA_TO_DEVICE);
2006 if (unlikely(dma_mapping_error(hp->dma_dev, mapping)))
2009 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2021 first_mapping = dma_map_single(hp->dma_dev, skb->data, first_len,
2023 if (unlikely(dma_mapping_error(hp->dma_dev, first_mapping)))
2032 mapping = skb_frag_dma_map(hp->dma_dev, this_frag,
2034 if (unlikely(dma_mapping_error(hp->dma_dev, mapping))) {
2035 unmap_partial_tx_skb(hp, first_mapping, first_len,
2042 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2047 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2052 hp->tx_new = entry;
2054 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2058 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2060 spin_unlock_irq(&hp->happy_lock);
2062 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2066 hp->tx_skbs[hp->tx_new] = NULL;
2067 spin_unlock_irq(&hp->happy_lock);
2076 struct happy_meal *hp = netdev_priv(dev);
2078 spin_lock_irq(&hp->happy_lock);
2079 happy_meal_get_counters(hp, hp->bigmacregs);
2080 spin_unlock_irq(&hp->happy_lock);
2087 struct happy_meal *hp = netdev_priv(dev);
2088 void __iomem *bregs = hp->bigmacregs;
2092 spin_lock_irq(&hp->happy_lock);
2095 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2096 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2097 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2098 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2100 hme_write32(hp, bregs + BMAC_RXCFG,
2101 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2111 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2112 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2113 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2114 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2117 spin_unlock_irq(&hp->happy_lock);
2124 struct happy_meal *hp = netdev_priv(dev);
2138 spin_lock_irq(&hp->happy_lock);
2139 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2140 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2141 spin_unlock_irq(&hp->happy_lock);
2143 if (hp->sw_bmcr & BMCR_ANENABLE) {
2145 speed = ((hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2149 (hp->sw_lpa & (LPA_100FULL)) ?
2153 (hp->sw_lpa & (LPA_10FULL)) ?
2157 speed = (hp->sw_bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
2159 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2172 struct happy_meal *hp = netdev_priv(dev);
2186 spin_lock_irq(&hp->happy_lock);
2187 del_timer(&hp->happy_timer);
2188 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
2189 spin_unlock_irq(&hp->happy_lock);
2196 struct happy_meal *hp = netdev_priv(dev);
2199 if (hp->happy_flags & HFLAG_PCI) {
2200 struct pci_dev *pdev = hp->happy_dev;
2206 struct platform_device *op = hp->happy_dev;
2218 struct happy_meal *hp = netdev_priv(dev);
2220 spin_lock_irq(&hp->happy_lock);
2221 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2222 spin_unlock_irq(&hp->happy_lock);
2224 return hp->sw_bmsr & BMSR_LSTATUS;
2392 static void happy_meal_addr_init(struct happy_meal *hp,
2407 eth_hw_addr_set(hp->dev, addr);
2420 eth_hw_addr_set(hp->dev, addr);
2425 eth_hw_addr_set(hp->dev, idprom->id_ethaddr);
2429 get_hme_mac_nonsparc(hp->happy_dev, addr);
2430 eth_hw_addr_set(hp->dev, addr);
2435 static int happy_meal_common_probe(struct happy_meal *hp,
2438 struct net_device *dev = hp->dev;
2442 hp->hm_revision = of_getintprop_default(dp, "hm-rev", hp->hm_revision);
2446 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2447 hp->happy_flags |= HFLAG_20_21;
2448 else if (hp->hm_revision != 0xa0)
2449 hp->happy_flags |= HFLAG_NOT_A0;
2451 hp->happy_block = dmam_alloc_coherent(hp->dma_dev, PAGE_SIZE,
2452 &hp->hblock_dvma, GFP_KERNEL);
2453 if (!hp->happy_block)
2457 hp->linkcheck = 0;
2460 hp->timer_state = asleep;
2461 hp->timer_ticks = 0;
2463 timer_setup(&hp->happy_timer, happy_meal_timer, 0);
2477 spin_lock_irq(&hp->happy_lock);
2478 happy_meal_set_initial_advertisement(hp);
2479 spin_unlock_irq(&hp->happy_lock);
2481 err = devm_register_netdev(hp->dma_dev, dev);
2483 dev_err(hp->dma_dev, "Cannot register net device, aborting.\n");
2492 struct happy_meal *hp;
2519 hp = netdev_priv(dev);
2520 hp->dev = dev;
2521 hp->happy_dev = op;
2522 hp->dma_dev = &op->dev;
2523 happy_meal_addr_init(hp, dp, qfe_slot);
2525 spin_lock_init(&hp->happy_lock);
2528 hp->qfe_parent = qp;
2529 hp->qfe_ent = qfe_slot;
2533 hp->gregs = devm_platform_ioremap_resource(op, 0);
2534 if (IS_ERR(hp->gregs)) {
2536 err = PTR_ERR(hp->gregs);
2540 hp->etxregs = devm_platform_ioremap_resource(op, 1);
2541 if (IS_ERR(hp->etxregs)) {
2543 err = PTR_ERR(hp->etxregs);
2547 hp->erxregs = devm_platform_ioremap_resource(op, 2);
2548 if (IS_ERR(hp->erxregs)) {
2550 err = PTR_ERR(hp->erxregs);
2554 hp->bigmacregs = devm_platform_ioremap_resource(op, 3);
2555 if (IS_ERR(hp->bigmacregs)) {
2557 err = PTR_ERR(hp->bigmacregs);
2561 hp->tcvregs = devm_platform_ioremap_resource(op, 4);
2562 if (IS_ERR(hp->tcvregs)) {
2564 err = PTR_ERR(hp->tcvregs);
2568 hp->hm_revision = 0xa0;
2571 hp->happy_flags |= HFLAG_QUATTRO;
2573 hp->irq = op->archdata.irqs[0];
2576 hp->happy_bursts = of_getintprop_default(sbus_dp,
2581 hp->read_desc32 = sbus_hme_read_desc32;
2582 hp->write_txd = sbus_hme_write_txd;
2583 hp->write_rxd = sbus_hme_write_rxd;
2584 hp->read32 = sbus_hme_read32;
2585 hp->write32 = sbus_hme_write32;
2588 err = happy_meal_common_probe(hp, dp);
2592 platform_set_drvdata(op, hp);
2617 struct happy_meal *hp;
2659 hp = netdev_priv(dev);
2660 hp->dev = dev;
2661 hp->happy_dev = pdev;
2662 hp->dma_dev = &pdev->dev;
2664 spin_lock_init(&hp->happy_lock);
2667 hp->qfe_parent = qp;
2668 hp->qfe_ent = qfe_slot;
2696 happy_meal_addr_init(hp, dp, qfe_slot);
2699 hp->gregs = (hpreg_base + 0x0000UL);
2700 hp->etxregs = (hpreg_base + 0x2000UL);
2701 hp->erxregs = (hpreg_base + 0x4000UL);
2702 hp->bigmacregs = (hpreg_base + 0x6000UL);
2703 hp->tcvregs = (hpreg_base + 0x7000UL);
2706 hp->hm_revision = 0xc0 | (pdev->revision & 0x0f);
2708 hp->hm_revision = 0x20;
2711 hp->happy_flags |= HFLAG_QUATTRO;
2714 hp->happy_flags |= HFLAG_PCI;
2718 hp->happy_bursts = DMA_BURSTBITS;
2720 hp->irq = pdev->irq;
2724 hp->read_desc32 = pci_hme_read_desc32;
2725 hp->write_txd = pci_hme_write_txd;
2726 hp->write_rxd = pci_hme_write_rxd;
2727 hp->read32 = pci_hme_read32;
2728 hp->write32 = pci_hme_write32;
2731 err = happy_meal_common_probe(hp, dp);
2735 pci_set_drvdata(pdev, hp);