stmicro/stmmac/stmmac_mdio.c

48 static void stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr,
54 	tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
56 	writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
62 static void stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr,
67 	if (priv->synopsys_id < DWXGMAC_CORE_2_20) {
71 		tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
76 	writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
81 static int stmmac_xgmac2_mdio_read(struct stmmac_priv *priv, u32 addr,
84 	unsigned int mii_address = priv->hw->mii.addr;
85 	unsigned int mii_data = priv->hw->mii.data;
89 	ret = pm_runtime_resume_and_get(priv->device);
94 	if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
100 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
101 		& priv->hw->mii.clk_csr_mask;
105 	if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
112 	writel(addr, priv->ioaddr + mii_address);
113 	writel(value, priv->ioaddr + mii_data);
116 	if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
123 	ret = (int)readl(priv->ioaddr + mii_data) & GENMASK(15, 0);
126 	pm_runtime_put(priv->device);
134 	struct net_device *ndev = bus->priv;
135 	struct stmmac_priv *priv;
138 	priv = netdev_priv(ndev);
141 	if (priv->synopsys_id < DWXGMAC_CORE_2_20 &&
145 	stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
147 	return stmmac_xgmac2_mdio_read(priv, addr, MII_XGMAC_BUSY);
153 	struct net_device *ndev = bus->priv;
154 	struct stmmac_priv *priv;
157 	priv = netdev_priv(ndev);
159 	stmmac_xgmac2_c45_format(priv, phyaddr, devad, phyreg, &addr);
161 	return stmmac_xgmac2_mdio_read(priv, addr, MII_XGMAC_BUSY);
164 static int stmmac_xgmac2_mdio_write(struct stmmac_priv *priv, u32 addr,
167 	unsigned int mii_address = priv->hw->mii.addr;
168 	unsigned int mii_data = priv->hw->mii.data;
172 	ret = pm_runtime_resume_and_get(priv->device);
177 	if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
183 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
184 		& priv->hw->mii.clk_csr_mask;
189 	if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
196 	writel(addr, priv->ioaddr + mii_address);
197 	writel(value, priv->ioaddr + mii_data);
200 	ret = readl_poll_timeout(priv->ioaddr + mii_data, tmp,
204 	pm_runtime_put(priv->device);
212 	struct net_device *ndev = bus->priv;
213 	struct stmmac_priv *priv;
216 	priv = netdev_priv(ndev);
219 	if (priv->synopsys_id < DWXGMAC_CORE_2_20 &&
223 	stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
225 	return stmmac_xgmac2_mdio_write(priv, addr,
232 	struct net_device *ndev = bus->priv;
233 	struct stmmac_priv *priv;
236 	priv = netdev_priv(ndev);
238 	stmmac_xgmac2_c45_format(priv, phyaddr, devad, phyreg, &addr);
240 	return stmmac_xgmac2_mdio_write(priv, addr, MII_XGMAC_BUSY,
244 static int stmmac_mdio_read(struct stmmac_priv *priv, int data, u32 value)
246 	unsigned int mii_address = priv->hw->mii.addr;
247 	unsigned int mii_data = priv->hw->mii.data;
250 	if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
254 	writel(data, priv->ioaddr + mii_data);
255 	writel(value, priv->ioaddr + mii_address);
257 	if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
262 	return readl(priv->ioaddr + mii_data) & MII_DATA_MASK;
277 	struct net_device *ndev = bus->priv;
278 	struct stmmac_priv *priv = netdev_priv(ndev);
282 	data = pm_runtime_resume_and_get(priv->device);
286 	value |= (phyaddr << priv->hw->mii.addr_shift)
287 		& priv->hw->mii.addr_mask;
288 	value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
289 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
290 		& priv->hw->mii.clk_csr_mask;
291 	if (priv->plat->has_gmac4)
294 	data = stmmac_mdio_read(priv, data, value);
296 	pm_runtime_put(priv->device);
315 	struct net_device *ndev = bus->priv;
316 	struct stmmac_priv *priv = netdev_priv(ndev);
320 	data = pm_runtime_get_sync(priv->device);
322 		pm_runtime_put_noidle(priv->device);
326 	value |= (phyaddr << priv->hw->mii.addr_shift)
327 		& priv->hw->mii.addr_mask;
328 	value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
329 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
330 		& priv->hw->mii.clk_csr_mask;
333 	value &= ~priv->hw->mii.reg_mask;
334 	value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
338 	data = stmmac_mdio_read(priv, data, value);
340 	pm_runtime_put(priv->device);
345 static int stmmac_mdio_write(struct stmmac_priv *priv, int data, u32 value)
347 	unsigned int mii_address = priv->hw->mii.addr;
348 	unsigned int mii_data = priv->hw->mii.data;
352 	if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
357 	writel(data, priv->ioaddr + mii_data);
358 	writel(value, priv->ioaddr + mii_address);
361 	return readl_poll_timeout(priv->ioaddr + mii_address, v,
376 	struct net_device *ndev = bus->priv;
377 	struct stmmac_priv *priv = netdev_priv(ndev);
381 	ret = pm_runtime_resume_and_get(priv->device);
385 	value |= (phyaddr << priv->hw->mii.addr_shift)
386 		& priv->hw->mii.addr_mask;
387 	value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
389 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
390 		& priv->hw->mii.clk_csr_mask;
391 	if (priv->plat->has_gmac4)
396 	ret = stmmac_mdio_write(priv, data, value);
398 	pm_runtime_put(priv->device);
415 	struct net_device *ndev = bus->priv;
416 	struct stmmac_priv *priv = netdev_priv(ndev);
420 	ret = pm_runtime_get_sync(priv->device);
422 		pm_runtime_put_noidle(priv->device);
426 	value |= (phyaddr << priv->hw->mii.addr_shift)
427 		& priv->hw->mii.addr_mask;
428 	value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
430 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
431 		& priv->hw->mii.clk_csr_mask;
435 	value &= ~priv->hw->mii.reg_mask;
436 	value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
440 	ret = stmmac_mdio_write(priv, data, value);
442 	pm_runtime_put(priv->device);
455 	struct net_device *ndev = bus->priv;
456 	struct stmmac_priv *priv = netdev_priv(ndev);
457 	unsigned int mii_address = priv->hw->mii.addr;
460 	if (priv->device->of_node) {
464 		reset_gpio = devm_gpiod_get_optional(priv->device,
470 		device_property_read_u32_array(priv->device,
492 	if (!priv->plat->has_gmac4)
493 		writel(0, priv->ioaddr + mii_address);
501 	struct stmmac_priv *priv;
505 	priv = netdev_priv(ndev);
506 	mode = priv->plat->phy_interface;
508 	if (priv->plat->pcs_init) {
509 		ret = priv->plat->pcs_init(priv);
510 	} else if (priv->plat->mdio_bus_data &&
511 		   priv->plat->mdio_bus_data->has_xpcs) {
514 			xpcs = xpcs_create_mdiodev(priv->mii, addr, mode);
526 		dev_warn(priv->device, "No xPCS found\n");
530 	priv->hw->xpcs = xpcs;
537 	struct stmmac_priv *priv = netdev_priv(ndev);
539 	if (priv->plat->pcs_exit)
540 		priv->plat->pcs_exit(priv);
542 	if (!priv->hw->xpcs)
545 	xpcs_destroy(priv->hw->xpcs);
546 	priv->hw->xpcs = NULL;
558 	struct stmmac_priv *priv = netdev_priv(ndev);
559 	struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
560 	struct device_node *mdio_node = priv->plat->mdio_node;
578 	if (priv->plat->has_xgmac) {
584 		if (priv->synopsys_id < DWXGMAC_CORE_2_20) {
589 			if (priv->plat->phy_addr > MII_XGMAC_MAX_C22ADDR)
599 		if (priv->plat->has_gmac4) {
611 		 new_bus->name, priv->plat->bus_id);
612 	new_bus->priv = ndev;
614 	new_bus->parent = priv->device;
627 	if (priv->plat->has_xgmac)
631 	fwnode = priv->plat->port_node;
633 		fwnode = dev_fwnode(priv->device);
643 	if (priv->plat->phy_node || mdio_node)
668 		if (priv->plat->phy_addr == -1)
669 			priv->plat->phy_addr = addr;
682 	priv->mii = new_bus;
700 	struct stmmac_priv *priv = netdev_priv(ndev);
702 	if (!priv->mii)
705 	mdiobus_unregister(priv->mii);
706 	priv->mii->priv = NULL;
707 	mdiobus_free(priv->mii);
708 	priv->mii = NULL;