stmicro/stmmac/stmmac_main.c

152 	int ret = 0;
155 		ret = clk_prepare_enable(priv->plat->stmmac_clk);
156 		if (ret)
157 			return ret;
158 		ret = clk_prepare_enable(priv->plat->pclk);
159 		if (ret) {
161 			return ret;
164 			ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled);
165 			if (ret) {
168 				return ret;
178 	return ret;
886 	int ret;
891 	ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE);
892 	if (ret)
893 		return ret;
1166 	int ret;
1198 		ret = phylink_connect_phy(priv->phylink, phydev);
1201 		ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0);
1212 	return ret;
1327 	int ret = bufsize;
1330 		ret = BUF_SIZE_16KiB;
1332 		ret = BUF_SIZE_8KiB;
1334 		ret = BUF_SIZE_4KiB;
1336 		ret = BUF_SIZE_2KiB;
1338 		ret = DEFAULT_BUFSIZE;
1340 	return ret;
1571 		int ret;
1578 		ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, flags,
1580 		if (ret)
1581 			return ret;
1673 	int ret;
1708 		ret = stmmac_alloc_rx_buffers(priv, dma_conf, queue, flags);
1709 		if (ret < 0)
1735 	int ret;
1742 		ret = __init_dma_rx_desc_rings(priv, dma_conf, queue, flags);
1743 		if (ret)
1764 	return ret;
1852 	int ret;
1854 	ret = init_dma_rx_desc_rings(dev, dma_conf, flags);
1855 	if (ret)
1856 		return ret;
1858 	ret = init_dma_tx_desc_rings(dev, dma_conf);
1865 	return ret;
2023 	int ret;
2040 		ret = PTR_ERR(rx_q->page_pool);
2042 		return ret;
2076 	ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev,
2079 	if (ret) {
2092 	int ret;
2096 		ret = __alloc_dma_rx_desc_resources(priv, dma_conf, queue);
2097 		if (ret)
2106 	return ret;
2171 	int ret;
2175 		ret = __alloc_dma_tx_desc_resources(priv, dma_conf, queue);
2176 		if (ret)
2184 	return ret;
2200 	int ret = alloc_dma_rx_desc_resources(priv, dma_conf);
2202 	if (ret)
2203 		return ret;
2205 	ret = alloc_dma_tx_desc_resources(priv, dma_conf);
2207 	return ret;
2857 	int ret;
2859 	ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2861 	if (ret && (ret != -EINVAL)) {
3010 	int ret = 0;
3020 	ret = stmmac_reset(priv, priv->ioaddr);
3021 	if (ret) {
3023 		return ret;
3064 	return ret;
3404 	int ret;
3411 	ret = stmmac_init_dma_engine(priv);
3412 	if (ret < 0) {
3415 		return ret;
3443 	ret = stmmac_rx_ipc(priv, priv->hw);
3444 	if (!ret) {
3459 		ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
3460 		if (ret < 0)
3463 				    ERR_PTR(ret));
3466 	ret = stmmac_init_ptp(priv);
3467 	if (ret == -EOPNOTSUPP)
3469 	else if (ret)
3618 	int ret;
3624 	ret = request_irq(dev->irq, stmmac_mac_interrupt,
3626 	if (unlikely(ret < 0)) {
3629 			   __func__, dev->irq, ret);
3641 		ret = request_irq(priv->wol_irq,
3644 		if (unlikely(ret < 0)) {
3647 				   __func__, priv->wol_irq, ret);
3659 		ret = request_irq(priv->lpi_irq,
3662 		if (unlikely(ret < 0)) {
3665 				   __func__, priv->lpi_irq, ret);
3677 		ret = request_irq(priv->sfty_irq, stmmac_safety_interrupt,
3679 		if (unlikely(ret < 0)) {
3682 				   __func__, priv->sfty_irq, ret);
3694 		ret = request_irq(priv->sfty_ce_irq,
3697 		if (unlikely(ret < 0)) {
3700 				   __func__, priv->sfty_ce_irq, ret);
3712 		ret = request_irq(priv->sfty_ue_irq,
3715 		if (unlikely(ret < 0)) {
3718 				   __func__, priv->sfty_ue_irq, ret);
3733 		ret = request_irq(priv->rx_irq[i],
3736 		if (unlikely(ret < 0)) {
3739 				   __func__, i, priv->rx_irq[i], ret);
3758 		ret = request_irq(priv->tx_irq[i],
3761 		if (unlikely(ret < 0)) {
3764 				   __func__, i, priv->tx_irq[i], ret);
3778 	return ret;
3785 	int ret;
3787 	ret = request_irq(dev->irq, stmmac_interrupt,
3789 	if (unlikely(ret < 0)) {
3792 			   __func__, dev->irq, ret);
3801 		ret = request_irq(priv->wol_irq, stmmac_interrupt,
3803 		if (unlikely(ret < 0)) {
3806 				   __func__, priv->wol_irq, ret);
3814 		ret = request_irq(priv->lpi_irq, stmmac_interrupt,
3816 		if (unlikely(ret < 0)) {
3819 				   __func__, priv->lpi_irq, ret);
3829 		ret = request_irq(priv->sfty_irq, stmmac_safety_interrupt,
3831 		if (unlikely(ret < 0)) {
3834 				   __func__, priv->sfty_irq, ret);
3844 	return ret;
3850 	int ret;
3854 		ret = stmmac_request_irq_multi_msi(dev);
3856 		ret = stmmac_request_irq_single(dev);
3858 	return ret;
3874 	int chan, bfsize, ret;
3911 	ret = alloc_dma_desc_resources(priv, dma_conf);
3912 	if (ret < 0) {
3918 	ret = init_dma_desc_rings(priv->dev, dma_conf, GFP_KERNEL);
3919 	if (ret < 0) {
3931 	return ERR_PTR(ret);
3950 	int ret;
3952 	ret = pm_runtime_resume_and_get(priv->device);
3953 	if (ret < 0)
3954 		return ret;
3960 		ret = stmmac_init_phy(dev);
3961 		if (ret) {
3964 				   __func__, ret);
3981 		ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv);
3982 		if (ret < 0) {
3989 	ret = stmmac_hw_setup(dev, true);
3990 	if (ret < 0) {
4001 	ret = stmmac_request_irq(dev);
4002 	if (ret)
4022 	return ret;
4029 	int ret;
4035 	ret = __stmmac_open(dev, dma_conf);
4036 	if (ret)
4040 	return ret;
5169 	bool ret = true;
5181 				ret = false;
5219 	return ret;
5869 	int ret;
5899 		ret = __stmmac_open(dev, dma_conf);
5900 		if (ret) {
5904 			return ret;
6198 	int ret = -EOPNOTSUPP;
6207 		ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
6210 		ret = stmmac_hwtstamp_set(dev, rq);
6213 		ret = stmmac_hwtstamp_get(dev, rq);
6219 	return ret;
6226 	int ret = -EOPNOTSUPP;
6229 		return ret;
6235 		ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
6238 		ret = stmmac_tc_setup_cls(priv, priv, type_data);
6245 	return ret;
6295 	int ret = 0;
6297 	ret = pm_runtime_resume_and_get(priv->device);
6298 	if (ret < 0)
6299 		return ret;
6301 	ret = eth_mac_addr(ndev, addr);
6302 	if (ret)
6310 	return ret;
6669 	int ret;
6671 	ret = pm_runtime_resume_and_get(priv->device);
6672 	if (ret < 0)
6673 		return ret;
6679 	ret = stmmac_vlan_update(priv, is_double);
6680 	if (ret) {
6686 		ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6687 		if (ret)
6693 	return ret;
6700 	int ret;
6702 	ret = pm_runtime_resume_and_get(priv->device);
6703 	if (ret < 0)
6704 		return ret;
6712 		ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6713 		if (ret)
6717 	ret = stmmac_vlan_update(priv, is_double);
6722 	return ret;
6801 	int ret;
6803 	ret = __alloc_dma_rx_desc_resources(priv, &priv->dma_conf, queue);
6804 	if (ret) {
6809 	ret = __init_dma_rx_desc_rings(priv, &priv->dma_conf, queue, GFP_KERNEL);
6810 	if (ret) {
6863 	int ret;
6865 	ret = __alloc_dma_tx_desc_resources(priv, &priv->dma_conf, queue);
6866 	if (ret) {
6871 	ret = __init_dma_tx_desc_rings(priv,  &priv->dma_conf, queue);
6872 	if (ret) {
6942 	int ret;
6944 	ret = alloc_dma_desc_resources(priv, &priv->dma_conf);
6945 	if (ret < 0) {
6951 	ret = init_dma_desc_rings(dev, &priv->dma_conf, GFP_KERNEL);
6952 	if (ret < 0) {
7017 	ret = stmmac_request_irq(dev);
7018 	if (ret)
7037 	return ret;
7191 	int ret;
7199 	ret = stmmac_hwif_init(priv);
7200 	if (ret)
7201 		return ret;
7265 		ret = priv->hwif_quirks(priv);
7266 		if (ret)
7267 			return ret;
7338 	int ret = 0, i;
7355 		ret = stmmac_open(dev);
7357 	return ret;
7363 	int ret = 0;
7372 		ret = stmmac_open(dev);
7374 	return ret;
7490 	int i, ret = 0;
7550 		ret = -ENOMEM;
7566 		ret = reset_control_assert(priv->plat->stmmac_rst);
7571 		if (ret == -ENOTSUPP)
7575 	ret = reset_control_deassert(priv->plat->stmmac_ahb_rst);
7576 	if (ret == -ENOTSUPP)
7578 			ERR_PTR(ret));
7584 	ret = stmmac_hw_init(priv);
7585 	if (ret)
7605 	ret = stmmac_tc_init(priv, priv);
7606 	if (!ret) {
7637 		ret = dma_set_mask_and_coherent(device,
7639 		if (!ret) {
7650 			ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
7651 			if (ret) {
7745 		ret = stmmac_mdio_register(ndev);
7746 		if (ret < 0) {
7747 			dev_err_probe(priv->device, ret,
7757 	ret = stmmac_pcs_setup(ndev);
7758 	if (ret)
7761 	ret = stmmac_phy_setup(priv);
7762 	if (ret) {
7763 		netdev_err(ndev, "failed to setup phy (%d)\n", ret);
7767 	ret = register_netdev(ndev);
7768 	if (ret) {
7770 			__func__, ret);
7786 	return ret;
7803 	return ret;
7968 	int ret;
7993 		ret = priv->plat->serdes_powerup(ndev,
7996 		if (ret < 0)
7997 			return ret;