stmicro/stmmac/dwxgmac2_core.c

379 	u32 val = 0x0;
382 		val |= XGMAC_PWRDWN | XGMAC_MGKPKTEN;
384 		val |= XGMAC_PWRDWN | XGMAC_GLBLUCAST | XGMAC_RWKPKTEN;
385 	if (val) {
391 	writel(val, ioaddr + XGMAC_PMT);
568 				  u32 val)
572 	writel(val, ioaddr + XGMAC_RSS_DATA);
1027 	u32 val = readl(ioaddr + XGMAC_MTL_OPMODE);
1029 	val &= ~XGMAC_FRPE;
1030 	writel(val, ioaddr + XGMAC_MTL_OPMODE);
1037 	u32 val;
1039 	val = readl(ioaddr + XGMAC_MTL_OPMODE);
1040 	val |= XGMAC_FRPE;
1041 	writel(val, ioaddr + XGMAC_MTL_OPMODE);
1050 	for (i = 0; i < (sizeof(entry->val) / sizeof(u32)); i++) {
1051 		int real_pos = pos * (sizeof(entry->val) / sizeof(u32)) + i;
1052 		u32 val;
1056 					 val, !(val & XGMAC_STARTBUSY), 1, 10000);
1061 		val = *((u32 *)&entry->val + i);
1062 		writel(val, ioaddr + XGMAC_MTL_RXP_IACC_DATA);
1065 		val = real_pos & XGMAC_ADDR;
1066 		writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
1069 		val |= XGMAC_WRRDN;
1070 		writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
1073 		val |= XGMAC_STARTBUSY;
1074 		writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
1078 					 val, !(val & XGMAC_STARTBUSY), 1, 10000);
1133 	u32 old_val, val;
1137 	val = old_val & ~XGMAC_CONFIG_RE;
1138 	writel(val, ioaddr + XGMAC_RX_CONFIG);
1162 			entry->val.af = 0;
1163 			entry->val.rf = 0;
1164 			entry->val.nc = 1;
1165 			entry->val.ok_index = nve + 2;
1201 	val = (nve << 16) & XGMAC_NPE;
1202 	val |= nve & XGMAC_NVE;
1203 	writel(val, ioaddr + XGMAC_MTL_RXP_CONTROL_STATUS);
1233 	u32 val = readl(ioaddr + XGMAC_PPS_CONTROL);
1243 	val &= ~XGMAC_PPSx_MASK(index);
1246 		val |= XGMAC_PPSCMDx(index, XGMAC_PPSCMD_STOP);
1247 		writel(val, ioaddr + XGMAC_PPS_CONTROL);
1251 	val |= XGMAC_PPSCMDx(index, XGMAC_PPSCMD_START);
1252 	val |= XGMAC_TRGTMODSELx(index, XGMAC_PPSCMD_START);
1265 	val |= XGMAC_PPSENx(index);
1290 	writel(val, ioaddr + XGMAC_PPS_CONTROL);
1294 static void dwxgmac2_sarc_configure(void __iomem *ioaddr, int val)
1299 	value |= val << XGMAC_CONFIG_SARC_SHIFT;