Lines Matching defs:val
464 u32 val;
466 val = readl(ioaddr + GMAC_VLAN_TAG);
467 val &= ~GMAC_VLAN_TAG_VID;
468 val |= GMAC_VLAN_TAG_ETV | vid;
470 writel(val, ioaddr + GMAC_VLAN_TAG);
479 u32 val;
486 val = readl(ioaddr + GMAC_VLAN_TAG);
487 val &= ~(GMAC_VLAN_TAG_CTRL_OFS_MASK |
490 val |= (index << GMAC_VLAN_TAG_CTRL_OFS_SHIFT) | GMAC_VLAN_TAG_CTRL_OB;
492 writel(val, ioaddr + GMAC_VLAN_TAG);
495 val = readl(ioaddr + GMAC_VLAN_TAG);
496 if (!(val & GMAC_VLAN_TAG_CTRL_OB))
511 u32 val = 0;
537 val |= GMAC_VLAN_TAG_DATA_ETV | GMAC_VLAN_TAG_DATA_VEN | vid;
540 if (hw->vlan_filter[i] == val)
552 ret = dwmac4_write_vlan_filter(dev, hw, index, val);
555 hw->vlan_filter[index] = val;
596 u32 val;
608 val = hw->vlan_filter[i];
609 dwmac4_write_vlan_filter(dev, hw, i, val);
1023 static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
1028 value |= val << GMAC_CONFIG_SARC_SHIFT;
1340 u32 val, num_vlan;
1342 val = readl(ioaddr + GMAC_HW_FEATURE3);
1343 switch (val & GMAC_HW_FEAT_NRVF) {