Lines Matching defs:ethqos
104 int (*configure_func)(struct qcom_ethqos *ethqos);
119 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
121 return readl(ethqos->rgmii_base + offset);
124 static void rgmii_writel(struct qcom_ethqos *ethqos,
127 writel(value, ethqos->rgmii_base + offset);
130 static void rgmii_updatel(struct qcom_ethqos *ethqos,
135 temp = rgmii_readl(ethqos, offset);
137 rgmii_writel(ethqos, temp, offset);
142 struct qcom_ethqos *ethqos = priv;
143 struct device *dev = ðqos->pdev->dev;
147 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
149 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
151 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
153 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
155 rgmii_readl(ethqos, SDC4_STATUS));
157 rgmii_readl(ethqos, SDCC_USR_CTL));
159 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
161 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
163 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
172 ethqos_update_link_clk(struct qcom_ethqos *ethqos, unsigned int speed)
174 if (!phy_interface_mode_is_rgmii(ethqos->phy_mode))
179 ethqos->link_clk_rate = RGMII_1000_NOM_CLK_FREQ;
183 ethqos->link_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
187 ethqos->link_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
191 clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate);
194 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
196 rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,
299 static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
301 struct device *dev = ðqos->pdev->dev;
306 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
310 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
314 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
318 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
321 if (!ethqos->has_emac_ge_3) {
322 rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
325 rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
331 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
342 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
348 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
359 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
362 if (!ethqos->has_emac_ge_3) {
363 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
366 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
369 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
372 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
380 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
382 struct device *dev = ðqos->pdev->dev;
387 if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID ||
388 ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID)
394 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
398 if (ethqos->rgmii_config_loopback_en)
404 rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL,
407 switch (ethqos->speed) {
409 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
411 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
413 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
416 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
418 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
421 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
423 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
425 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
432 if (ethqos->has_emac_ge_3) {
434 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
438 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
441 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
444 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
449 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
451 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
454 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
456 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
458 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
460 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
462 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
464 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
467 if (ethqos->has_emac_ge_3)
468 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
472 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
476 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
478 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
481 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
484 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
489 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
491 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
494 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
496 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
498 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
500 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
502 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
505 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
507 if (ethqos->has_emac_ge_3)
508 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
512 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
515 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
517 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
520 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
523 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
527 dev_err(dev, "Invalid speed %d\n", ethqos->speed);
534 static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos)
536 struct device *dev = ðqos->pdev->dev;
541 for (i = 0; i < ethqos->num_por; i++)
542 rgmii_writel(ethqos, ethqos->por[i].value,
543 ethqos->por[i].offset);
544 ethqos_set_func_clk_en(ethqos);
549 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST,
553 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
556 if (ethqos->has_emac_ge_3) {
557 if (ethqos->speed == SPEED_1000) {
558 rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL);
559 rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL);
560 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2);
562 rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL);
563 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2);
568 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,
572 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0,
575 if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) {
577 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
581 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
586 if (!ethqos->has_emac_ge_3)
587 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26),
593 dll_lock = rgmii_readl(ethqos, SDC4_STATUS);
602 if (ethqos->speed == SPEED_1000)
603 ethqos_dll_configure(ethqos);
605 ethqos_rgmii_macro_init(ethqos);
613 static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
615 struct net_device *dev = platform_get_drvdata(ethqos->pdev);
619 val = readl(ethqos->mac_base + MAC_CTRL_REG);
621 switch (ethqos->speed) {
624 rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
627 if (ethqos->serdes_speed != SPEED_2500)
628 phy_set_speed(ethqos->serdes_phy, SPEED_2500);
629 ethqos->serdes_speed = SPEED_2500;
634 rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
637 if (ethqos->serdes_speed != SPEED_1000)
638 phy_set_speed(ethqos->serdes_phy, SPEED_1000);
639 ethqos->serdes_speed = SPEED_1000;
644 if (ethqos->serdes_speed != SPEED_1000)
645 phy_set_speed(ethqos->serdes_phy, SPEED_1000);
646 ethqos->serdes_speed = SPEED_1000;
652 rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR,
656 if (ethqos->serdes_speed != SPEED_1000)
657 phy_set_speed(ethqos->serdes_phy, ethqos->speed);
658 ethqos->serdes_speed = SPEED_1000;
663 writel(val, ethqos->mac_base + MAC_CTRL_REG);
668 static int ethqos_configure(struct qcom_ethqos *ethqos)
670 return ethqos->configure_func(ethqos);
675 struct qcom_ethqos *ethqos = priv;
677 ethqos->speed = speed;
678 ethqos_update_link_clk(ethqos, speed);
679 ethqos_configure(ethqos);
684 struct qcom_ethqos *ethqos = priv;
687 ret = phy_init(ethqos->serdes_phy);
691 ret = phy_power_on(ethqos->serdes_phy);
695 return phy_set_speed(ethqos->serdes_phy, ethqos->speed);
700 struct qcom_ethqos *ethqos = priv;
702 phy_power_off(ethqos->serdes_phy);
703 phy_exit(ethqos->serdes_phy);
708 struct qcom_ethqos *ethqos = priv;
712 ret = clk_prepare_enable(ethqos->link_clk);
714 dev_err(ðqos->pdev->dev, "link_clk enable failed\n");
723 ethqos_set_func_clk_en(ethqos);
725 clk_disable_unprepare(ethqos->link_clk);
760 struct qcom_ethqos *ethqos;
776 ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL);
777 if (!ethqos)
780 ret = of_get_phy_mode(np, ðqos->phy_mode);
783 switch (ethqos->phy_mode) {
788 ethqos->configure_func = ethqos_configure_rgmii;
791 ethqos->configure_func = ethqos_configure_sgmii;
795 phy_modes(ethqos->phy_mode));
799 ethqos->pdev = pdev;
800 ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii");
801 if (IS_ERR(ethqos->rgmii_base))
802 return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base),
805 ethqos->mac_base = stmmac_res.addr;
808 ethqos->por = data->por;
809 ethqos->num_por = data->num_por;
810 ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en;
811 ethqos->has_emac_ge_3 = data->has_emac_ge_3;
813 ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii");
814 if (IS_ERR(ethqos->link_clk))
815 return dev_err_probe(dev, PTR_ERR(ethqos->link_clk),
818 ret = ethqos_clks_config(ethqos, true);
822 ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos);
826 ethqos->serdes_phy = devm_phy_optional_get(dev, "serdes");
827 if (IS_ERR(ethqos->serdes_phy))
828 return dev_err_probe(dev, PTR_ERR(ethqos->serdes_phy),
831 ethqos->speed = SPEED_1000;
832 ethqos->serdes_speed = SPEED_1000;
833 ethqos_update_link_clk(ethqos, SPEED_1000);
834 ethqos_set_func_clk_en(ethqos);
836 plat_dat->bsp_priv = ethqos;
841 if (ethqos->has_emac_ge_3)
846 if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))
853 if (ethqos->serdes_phy) {
866 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
867 { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data},
868 { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data},
869 { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
877 .name = "qcom-ethqos",