Lines Matching refs:pd
87 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
89 return ioread32(pd->ioaddr + offset);
93 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
95 iowrite32(value, pd->ioaddr + offset);
98 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
101 smsc9420_reg_read(pd, ID_REV);
106 struct smsc9420_pdata *pd = bus->priv;
111 spin_lock_irqsave(&pd->phy_lock, flags);
114 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
115 netif_warn(pd, drv, pd->dev, "MII is busy???\n");
122 smsc9420_reg_write(pd, MII_ACCESS, addr);
126 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
128 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
134 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
137 spin_unlock_irqrestore(&pd->phy_lock, flags);
144 struct smsc9420_pdata *pd = bus->priv;
149 spin_lock_irqsave(&pd->phy_lock, flags);
152 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
153 netif_warn(pd, drv, pd->dev, "MII is busy???\n");
158 smsc9420_reg_write(pd, MII_DATA, (u32)val);
163 smsc9420_reg_write(pd, MII_ACCESS, addr);
167 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
175 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
178 spin_unlock_irqrestore(&pd->phy_lock, flags);
190 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
194 BUG_ON(!pd);
196 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
197 netif_dbg(pd, drv, pd->dev, "%s: Eeprom busy\n", __func__);
201 smsc9420_reg_write(pd, E2P_CMD,
206 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
210 netif_warn(pd, drv, pd->dev, "%s: Eeprom timed out\n", __func__);
217 struct smsc9420_pdata *pd = netdev_priv(netdev);
220 strscpy(drvinfo->bus_info, pci_name(pd->pdev),
227 struct smsc9420_pdata *pd = netdev_priv(netdev);
228 return pd->msg_enable;
233 struct smsc9420_pdata *pd = netdev_priv(netdev);
234 pd->msg_enable = data;
247 struct smsc9420_pdata *pd = netdev_priv(dev);
252 regs->version = smsc9420_reg_read(pd, ID_REV);
254 data[j++] = smsc9420_reg_read(pd, i);
265 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
267 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
269 smsc9420_reg_write(pd, GPIO_CFG, temp);
273 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
278 netif_dbg(pd, hw, pd->dev, "op 0x%08x\n", op);
279 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
280 netif_warn(pd, hw, pd->dev, "Busy at start\n");
285 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
289 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
293 netif_info(pd, hw, pd->dev, "TIMED OUT\n");
298 netif_info(pd, hw, pd->dev,
306 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
312 netif_dbg(pd, hw, pd->dev, "address 0x%x\n", address);
313 ret = smsc9420_eeprom_send_cmd(pd, op);
316 data[address] = smsc9420_reg_read(pd, E2P_DATA);
321 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
327 netif_dbg(pd, hw, pd->dev, "address 0x%x, data 0x%x\n", address, data);
328 ret = smsc9420_eeprom_send_cmd(pd, op);
332 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
333 ret = smsc9420_eeprom_send_cmd(pd, op);
347 struct smsc9420_pdata *pd = netdev_priv(dev);
351 smsc9420_eeprom_enable_access(pd);
355 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
371 struct smsc9420_pdata *pd = netdev_priv(dev);
377 smsc9420_eeprom_enable_access(pd);
378 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
379 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
380 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
407 struct smsc9420_pdata *pd = netdev_priv(dev);
413 smsc9420_reg_write(pd, ADDRH, mac_high16);
414 smsc9420_reg_write(pd, ADDRL, mac_low32);
419 struct smsc9420_pdata *pd = netdev_priv(dev);
425 netif_dbg(pd, probe, pd->dev,
430 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
431 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
442 netif_dbg(pd, probe, pd->dev,
448 netif_dbg(pd, probe, pd->dev,
454 static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
460 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
462 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
466 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
472 netif_warn(pd, ifdown, pd->dev, "TX DMAC failed to stop\n");
475 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
478 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
480 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
481 smsc9420_pci_flush_write(pd);
484 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
485 smsc9420_reg_write(pd, MAC_CR, mac_cr);
486 smsc9420_pci_flush_write(pd);
489 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
493 BUG_ON(!pd->tx_ring);
495 if (!pd->tx_buffers)
499 struct sk_buff *skb = pd->tx_buffers[i].skb;
502 BUG_ON(!pd->tx_buffers[i].mapping);
503 dma_unmap_single(&pd->pdev->dev,
504 pd->tx_buffers[i].mapping, skb->len,
509 pd->tx_ring[i].status = 0;
510 pd->tx_ring[i].length = 0;
511 pd->tx_ring[i].buffer1 = 0;
512 pd->tx_ring[i].buffer2 = 0;
516 kfree(pd->tx_buffers);
517 pd->tx_buffers = NULL;
519 pd->tx_ring_head = 0;
520 pd->tx_ring_tail = 0;
523 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
527 BUG_ON(!pd->rx_ring);
529 if (!pd->rx_buffers)
533 if (pd->rx_buffers[i].skb)
534 dev_kfree_skb_any(pd->rx_buffers[i].skb);
536 if (pd->rx_buffers[i].mapping)
537 dma_unmap_single(&pd->pdev->dev,
538 pd->rx_buffers[i].mapping,
541 pd->rx_ring[i].status = 0;
542 pd->rx_ring[i].length = 0;
543 pd->rx_ring[i].buffer1 = 0;
544 pd->rx_ring[i].buffer2 = 0;
548 kfree(pd->rx_buffers);
549 pd->rx_buffers = NULL;
551 pd->rx_ring_head = 0;
552 pd->rx_ring_tail = 0;
555 static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
561 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
563 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
564 smsc9420_pci_flush_write(pd);
567 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
568 smsc9420_reg_write(pd, MAC_CR, mac_cr);
569 smsc9420_pci_flush_write(pd);
572 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
574 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
575 smsc9420_pci_flush_write(pd);
579 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
585 netif_warn(pd, ifdown, pd->dev,
589 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
594 struct smsc9420_pdata *pd = dev_id;
599 BUG_ON(!pd);
600 BUG_ON(!pd->ioaddr);
602 int_cfg = smsc9420_reg_read(pd, INT_CFG);
609 int_sts = smsc9420_reg_read(pd, INT_STAT);
612 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
617 netif_wake_queue(pd->dev);
622 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
624 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
625 smsc9420_pci_flush_write(pd);
628 napi_schedule(&pd->napi);
632 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
639 spin_lock_irqsave(&pd->int_lock, flags);
640 int_ctl = smsc9420_reg_read(pd, INT_CTL);
642 smsc9420_reg_write(pd, INT_CTL, int_ctl);
643 spin_unlock_irqrestore(&pd->int_lock, flags);
645 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
646 pd->software_irq_signal = true;
653 smsc9420_pci_flush_write(pd);
661 struct smsc9420_pdata *pd = netdev_priv(dev);
662 const int irq = pd->pdev->irq;
670 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
672 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
673 smsc9420_reg_read(pd, BUS_MODE);
675 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
676 netif_warn(pd, drv, pd->dev, "Software reset not cleared\n");
681 struct smsc9420_pdata *pd = netdev_priv(dev);
685 BUG_ON(!pd);
689 spin_lock_irqsave(&pd->int_lock, flags);
690 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
691 smsc9420_reg_write(pd, INT_CFG, int_cfg);
692 spin_unlock_irqrestore(&pd->int_lock, flags);
695 napi_disable(&pd->napi);
697 smsc9420_stop_tx(pd);
698 smsc9420_free_tx_ring(pd);
700 smsc9420_stop_rx(pd);
701 smsc9420_free_rx_ring(pd);
703 free_irq(pd->pdev->irq, pd);
705 smsc9420_dmac_soft_reset(pd);
710 mdiobus_unregister(pd->mii_bus);
711 mdiobus_free(pd->mii_bus);
740 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
743 struct net_device *dev = pd->dev;
751 if (pd->rx_csum)
757 dma_unmap_single(&pd->pdev->dev, pd->rx_buffers[index].mapping,
759 pd->rx_buffers[index].mapping = 0;
761 skb = pd->rx_buffers[index].skb;
762 pd->rx_buffers[index].skb = NULL;
764 if (pd->rx_csum) {
779 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
781 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
784 BUG_ON(pd->rx_buffers[index].skb);
785 BUG_ON(pd->rx_buffers[index].mapping);
790 mapping = dma_map_single(&pd->pdev->dev, skb_tail_pointer(skb),
792 if (dma_mapping_error(&pd->pdev->dev, mapping)) {
794 netif_warn(pd, rx_err, pd->dev, "dma_map_single failed!\n");
798 pd->rx_buffers[index].skb = skb;
799 pd->rx_buffers[index].mapping = mapping;
800 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
801 pd->rx_ring[index].status = RDES0_OWN_;
807 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
809 while (pd->rx_ring_tail != pd->rx_ring_head) {
810 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
813 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
819 struct smsc9420_pdata *pd =
821 struct net_device *dev = pd->dev;
827 status = pd->rx_ring[pd->rx_ring_head].status;
834 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
835 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
836 smsc9420_alloc_new_rx_buffers(pd);
839 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
844 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
845 smsc9420_pci_flush_write(pd);
848 napi_complete_done(&pd->napi, work_done);
851 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
853 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
854 smsc9420_pci_flush_write(pd);
890 struct smsc9420_pdata *pd = netdev_priv(dev);
892 while (pd->tx_ring_tail != pd->tx_ring_head) {
893 int index = pd->tx_ring_tail;
897 status = pd->tx_ring[index].status;
898 length = pd->tx_ring[index].length;
906 BUG_ON(!pd->tx_buffers[index].skb);
907 BUG_ON(!pd->tx_buffers[index].mapping);
909 dma_unmap_single(&pd->pdev->dev,
910 pd->tx_buffers[index].mapping,
911 pd->tx_buffers[index].skb->len,
913 pd->tx_buffers[index].mapping = 0;
915 dev_kfree_skb_any(pd->tx_buffers[index].skb);
916 pd->tx_buffers[index].skb = NULL;
918 pd->tx_ring[index].buffer1 = 0;
921 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
928 struct smsc9420_pdata *pd = netdev_priv(dev);
930 int index = pd->tx_ring_head;
933 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
938 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
939 BUG_ON(pd->tx_buffers[index].skb);
940 BUG_ON(pd->tx_buffers[index].mapping);
942 mapping = dma_map_single(&pd->pdev->dev, skb->data, skb->len,
944 if (dma_mapping_error(&pd->pdev->dev, mapping)) {
945 netif_warn(pd, tx_err, pd->dev,
950 pd->tx_buffers[index].skb = skb;
951 pd->tx_buffers[index].mapping = mapping;
956 netif_stop_queue(pd->dev);
963 pd->tx_ring[index].buffer1 = mapping;
964 pd->tx_ring[index].length = tmp_desc1;
968 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
971 pd->tx_ring[index].status = TDES0_OWN_;
977 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
978 smsc9420_pci_flush_write(pd);
985 struct smsc9420_pdata *pd = netdev_priv(dev);
986 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
994 struct smsc9420_pdata *pd = netdev_priv(dev);
995 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
998 netif_dbg(pd, hw, pd->dev, "Promiscuous Mode Enabled\n");
1003 netif_dbg(pd, hw, pd->dev, "Receive all Multicast Enabled\n");
1011 netif_dbg(pd, hw, pd->dev, "Multicast filter enabled\n");
1022 smsc9420_reg_write(pd, HASHH, hash_hi);
1023 smsc9420_reg_write(pd, HASHL, hash_lo);
1029 netif_dbg(pd, hw, pd->dev, "Receive own packets only\n");
1030 smsc9420_reg_write(pd, HASHH, 0);
1031 smsc9420_reg_write(pd, HASHL, 0);
1038 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1039 smsc9420_pci_flush_write(pd);
1042 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1044 struct net_device *dev = pd->dev;
1058 netif_info(pd, link, pd->dev, "rx pause %s, tx pause %s\n",
1062 netif_info(pd, link, pd->dev, "half duplex\n");
1066 smsc9420_reg_write(pd, FLOW, flow);
1073 struct smsc9420_pdata *pd = netdev_priv(dev);
1077 if (phy_dev->duplex != pd->last_duplex) {
1078 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1080 netif_dbg(pd, link, pd->dev, "full duplex mode\n");
1083 netif_dbg(pd, link, pd->dev, "half duplex mode\n");
1086 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1088 smsc9420_phy_update_flowcontrol(pd);
1089 pd->last_duplex = phy_dev->duplex;
1093 if (carrier != pd->last_carrier) {
1095 netif_dbg(pd, link, pd->dev, "carrier OK\n");
1097 netif_dbg(pd, link, pd->dev, "no carrier\n");
1098 pd->last_carrier = carrier;
1104 struct smsc9420_pdata *pd = netdev_priv(dev);
1110 phydev = mdiobus_get_phy(pd->mii_bus, 1);
1131 pd->last_duplex = -1;
1132 pd->last_carrier = -1;
1139 struct smsc9420_pdata *pd = netdev_priv(dev);
1142 pd->mii_bus = mdiobus_alloc();
1143 if (!pd->mii_bus) {
1147 pd->mii_bus->name = DRV_MDIONAME;
1148 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x", pci_dev_id(pd->pdev));
1149 pd->mii_bus->priv = pd;
1150 pd->mii_bus->read = smsc9420_mii_read;
1151 pd->mii_bus->write = smsc9420_mii_write;
1154 pd->mii_bus->phy_mask = ~(1 << 1);
1156 if (mdiobus_register(pd->mii_bus)) {
1157 netif_warn(pd, probe, pd->dev, "Error registering mii bus\n");
1162 netif_warn(pd, probe, pd->dev, "Error probing mii bus\n");
1169 mdiobus_unregister(pd->mii_bus);
1171 mdiobus_free(pd->mii_bus);
1176 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1180 BUG_ON(!pd->tx_ring);
1182 pd->tx_buffers = kmalloc_array(TX_RING_SIZE,
1185 if (!pd->tx_buffers)
1190 pd->tx_buffers[i].skb = NULL;
1191 pd->tx_buffers[i].mapping = 0;
1192 pd->tx_ring[i].status = 0;
1193 pd->tx_ring[i].length = 0;
1194 pd->tx_ring[i].buffer1 = 0;
1195 pd->tx_ring[i].buffer2 = 0;
1197 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1200 pd->tx_ring_head = 0;
1201 pd->tx_ring_tail = 0;
1203 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1204 smsc9420_pci_flush_write(pd);
1209 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1213 BUG_ON(!pd->rx_ring);
1215 pd->rx_buffers = kmalloc_array(RX_RING_SIZE,
1218 if (pd->rx_buffers == NULL)
1223 pd->rx_ring[i].status = 0;
1224 pd->rx_ring[i].length = PKT_BUF_SZ;
1225 pd->rx_ring[i].buffer2 = 0;
1226 pd->rx_buffers[i].skb = NULL;
1227 pd->rx_buffers[i].mapping = 0;
1229 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1233 if (smsc9420_alloc_rx_buffer(pd, i)) {
1234 netif_warn(pd, ifup, pd->dev,
1240 pd->rx_ring_head = 0;
1241 pd->rx_ring_tail = 0;
1243 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1244 netif_dbg(pd, ifup, pd->dev, "VLAN1 = 0x%08x\n",
1245 smsc9420_reg_read(pd, VLAN1));
1247 if (pd->rx_csum) {
1249 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1250 smsc9420_reg_write(pd, COE_CR, coe);
1251 netif_dbg(pd, ifup, pd->dev, "COE_CR = 0x%08x\n", coe);
1254 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1255 smsc9420_pci_flush_write(pd);
1260 smsc9420_free_rx_ring(pd);
1267 struct smsc9420_pdata *pd = netdev_priv(dev);
1269 const int irq = pd->pdev->irq;
1274 netif_warn(pd, ifup, pd->dev,
1283 spin_lock_irqsave(&pd->int_lock, flags);
1284 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1285 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1286 smsc9420_reg_write(pd, INT_CTL, 0);
1287 spin_unlock_irqrestore(&pd->int_lock, flags);
1288 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1289 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1290 smsc9420_pci_flush_write(pd);
1292 result = request_irq(irq, smsc9420_isr, IRQF_SHARED, DRV_NAME, pd);
1294 netif_warn(pd, ifup, pd->dev, "Unable to use IRQ = %d\n", irq);
1299 smsc9420_dmac_soft_reset(pd);
1302 smsc9420_reg_write(pd, MAC_CR, 0);
1307 smsc9420_reg_write(pd, GPIO_CFG,
1316 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1318 smsc9420_pci_flush_write(pd);
1321 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1323 smsc9420_reg_write(pd, DMAC_CONTROL,
1326 smsc9420_pci_flush_write(pd);
1329 netif_dbg(pd, ifup, pd->dev, "Testing ISR using IRQ %d\n", irq);
1330 pd->software_irq_signal = false;
1332 spin_lock_irqsave(&pd->int_lock, flags);
1334 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1337 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1340 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1341 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1342 spin_unlock_irqrestore(&pd->int_lock, flags);
1343 smsc9420_pci_flush_write(pd);
1347 if (pd->software_irq_signal)
1353 spin_lock_irqsave(&pd->int_lock, flags);
1354 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1355 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1356 spin_unlock_irqrestore(&pd->int_lock, flags);
1358 if (!pd->software_irq_signal) {
1359 netif_warn(pd, ifup, pd->dev, "ISR failed signaling test\n");
1364 netif_dbg(pd, ifup, pd->dev, "ISR passed test using IRQ %d\n", irq);
1366 result = smsc9420_alloc_tx_ring(pd);
1368 netif_warn(pd, ifup, pd->dev,
1374 result = smsc9420_alloc_rx_ring(pd);
1376 netif_warn(pd, ifup, pd->dev,
1384 netif_warn(pd, ifup, pd->dev, "Failed to initialize Phy\n");
1392 napi_enable(&pd->napi);
1395 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1396 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1398 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1400 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1401 smsc9420_pci_flush_write(pd);
1403 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1406 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1407 smsc9420_pci_flush_write(pd);
1411 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1414 spin_lock_irqsave(&pd->int_lock, flags);
1415 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1416 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1417 spin_unlock_irqrestore(&pd->int_lock, flags);
1422 smsc9420_free_rx_ring(pd);
1424 smsc9420_free_tx_ring(pd);
1426 free_irq(irq, pd);
1434 struct smsc9420_pdata *pd = netdev_priv(dev);
1439 spin_lock_irqsave(&pd->int_lock, flags);
1440 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1441 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1442 spin_unlock_irqrestore(&pd->int_lock, flags);
1446 smsc9420_stop_tx(pd);
1447 smsc9420_free_tx_ring(pd);
1449 napi_disable(&pd->napi);
1450 smsc9420_stop_rx(pd);
1451 smsc9420_free_rx_ring(pd);
1453 free_irq(pd->pdev->irq, pd);
1499 struct smsc9420_pdata *pd;
1515 dev = alloc_etherdev(sizeof(*pd));
1546 pd = netdev_priv(dev);
1549 pd->rx_ring = dma_alloc_coherent(&pdev->dev,
1551 &pd->rx_dma_addr, GFP_KERNEL);
1553 if (!pd->rx_ring)
1557 pd->tx_ring = (pd->rx_ring + RX_RING_SIZE);
1558 pd->tx_dma_addr = pd->rx_dma_addr +
1561 pd->pdev = pdev;
1562 pd->dev = dev;
1563 pd->ioaddr = virt_addr;
1564 pd->msg_enable = smsc_debug;
1565 pd->rx_csum = true;
1567 netif_dbg(pd, probe, pd->dev, "lan_base=0x%08lx\n", (ulong)virt_addr);
1569 id_rev = smsc9420_reg_read(pd, ID_REV);
1572 netif_info(pd, probe, pd->dev,
1576 netif_warn(pd, probe, pd->dev, "LAN9420 NOT identified\n");
1577 netif_warn(pd, probe, pd->dev, "ID_REV=0x%08X\n", id_rev);
1581 smsc9420_dmac_soft_reset(pd);
1582 smsc9420_eeprom_reload(pd);
1588 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll);
1592 netif_warn(pd, probe, pd->dev, "error %i registering device\n",
1599 spin_lock_init(&pd->int_lock);
1600 spin_lock_init(&pd->phy_lock);
1609 pd->rx_ring, pd->rx_dma_addr);
1625 struct smsc9420_pdata *pd;
1631 pd = netdev_priv(dev);
1635 BUG_ON(pd->tx_buffers);
1636 BUG_ON(pd->rx_buffers);
1638 BUG_ON(!pd->tx_ring);
1639 BUG_ON(!pd->rx_ring);
1643 pd->rx_ring, pd->rx_dma_addr);
1645 iounmap(pd->ioaddr - LAN9420_CPSR_ENDIAN_OFFSET);