ethernet/silan/sc92031.c

266 	void __iomem		*port_base;
309 static inline void _sc92031_dummy_read(void __iomem *port_base)
311 	ioread32(port_base + MAC0);
314 static u32 _sc92031_mii_wait(void __iomem *port_base)
320 		mii_status = ioread32(port_base + Miistatus);
326 static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)
328 	iowrite32(Mii_Divider, port_base + Miicmd0);
330 	_sc92031_mii_wait(port_base);
332 	iowrite32(cmd1, port_base + Miicmd1);
333 	iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);
335 	return _sc92031_mii_wait(port_base);
338 static void _sc92031_mii_scan(void __iomem *port_base)
340 	_sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);
343 static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)
345 	return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;
348 static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)
350 	_sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));
356 	void __iomem *port_base = priv->port_base;
363 	iowrite32(0, port_base + IntrMask);
364 	_sc92031_dummy_read(port_base);
374 	void __iomem *port_base = priv->port_base;
381 	iowrite32(IntrBits, port_base + IntrMask);
387 	void __iomem *port_base = priv->port_base;
391 	iowrite32(priv->rx_config, port_base + RxConfig);
392 	iowrite32(priv->tx_config, port_base + TxConfig);
398 	void __iomem *port_base = priv->port_base;
402 	iowrite32(priv->rx_config, port_base + RxConfig);
403 	iowrite32(priv->tx_config, port_base + TxConfig);
420 	void __iomem *port_base = priv->port_base;
451 	iowrite32(mar0, port_base + MAR0);
452 	iowrite32(mar1, port_base + MAR0 + 4);
458 	void __iomem *port_base = priv->port_base;
482 		iowrite32(priv->rx_config, port_base + RxConfig);
488 	void __iomem *port_base = priv->port_base;
491 	bmsr = _sc92031_mii_read(port_base, MII_BMSR);
496 		u16 output_status = _sc92031_mii_read(port_base,
498 		_sc92031_mii_scan(port_base);
527 		iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);
538 		_sc92031_mii_scan(port_base);
553 	void __iomem *port_base = priv->port_base;
556 	phy_ctrl = ioread32(port_base + PhyCtrl);
579 	iowrite32(phy_ctrl, port_base + PhyCtrl);
583 	iowrite32(phy_ctrl, port_base + PhyCtrl);
586 	_sc92031_mii_write(port_base, MII_JAB,
588 	_sc92031_mii_scan(port_base);
597 	void __iomem *port_base = priv->port_base;
600 	iowrite32(0, port_base + PMConfig);
603 	iowrite32(Cfg0_Reset, port_base + Config0);
606 	iowrite32(0, port_base + Config0);
610 	iowrite32(0, port_base + IntrMask);
613 	iowrite32(0, port_base + MAR0);
614 	iowrite32(0, port_base + MAR0 + 4);
617 	iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);
632 	iowrite32(Cfg1_Rcv64K, port_base + Config1);
641 	iowrite32(priv->pm_config, port_base + PMConfig);
644 	ioread32(port_base + IntrStatus);
650 	void __iomem *port_base = priv->port_base;
659 		tx_status = ioread32(port_base + TxStatus0 + entry * 4);
723 	void __iomem *port_base = priv->port_base;
730 	rx_ring_head = ioread32(port_base + RxBufWPtr);
820 	iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);
837 	void __iomem *port_base = priv->port_base;
868 	iowrite32(intr_mask, port_base + IntrMask);
877 	void __iomem *port_base = priv->port_base;
881 	iowrite32(0, port_base + IntrMask);
882 	_sc92031_dummy_read(port_base);
884 	intr_status = ioread32(port_base + IntrStatus);
901 	iowrite32(intr_mask, port_base + IntrMask);
909 	void __iomem *port_base = priv->port_base;
918 		temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;
936 	void __iomem *port_base = priv->port_base;
976 			port_base + TxAddr0 + entry * 4);
977 	iowrite32(tx_status, port_base + TxStatus0 + entry * 4);
1122 	void __iomem *port_base = priv->port_base;
1130 	phy_address = ioread32(port_base + Miicmd1) >> 27;
1131 	phy_ctrl = ioread32(port_base + PhyCtrl);
1133 	output_status = _sc92031_mii_read(port_base, MII_OutputStatus);
1134 	_sc92031_mii_scan(port_base);
1185 	void __iomem *port_base = priv->port_base;
1243 	old_phy_ctrl = ioread32(port_base + PhyCtrl);
1247 		iowrite32(phy_ctrl, port_base + PhyCtrl);
1258 	void __iomem *port_base = priv->port_base;
1262 	pm_config = ioread32(port_base + PMConfig);
1285 	void __iomem *port_base = priv->port_base;
1290 	pm_config = ioread32(port_base + PMConfig)
1304 	iowrite32(pm_config, port_base + PMConfig);
1315 	void __iomem *port_base = priv->port_base;
1320 	bmcr = _sc92031_mii_read(port_base, MII_BMCR);
1326 	_sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
1329 	_sc92031_mii_scan(port_base);
1400 	void __iomem* port_base;
1424 	port_base = pci_iomap(pdev, SC92031_USE_PIO, 0);
1425 	if (unlikely(!port_base)) {
1450 	priv->port_base = port_base;
1458 	iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);
1460 	mac0 = ioread32(port_base + MAC0);
1461 	mac1 = ioread32(port_base + MAC0 + 4);
1483 	pci_iounmap(pdev, port_base);
1497 	void __iomem* port_base = priv->port_base;
1501 	pci_iounmap(pdev, port_base);